Structure and method for reducing charge loss in a memory cell

Details Structure and method for reducing charge loss in a memory cell Structure and method for reducing charge loss in a memory cell

2002-12-05

2004-05-18

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S314000

Reexamination Certificate

active

06737701

ABSTRACT:

TECHNICAL FIELD
The present invention is generally related to the field semiconductor devices. More particularly, the present invention is related to memory cells in semiconductor devices.
BACKGROUND ART
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only-memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash memory devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash memory devices enable the erasing of all memory cells in the device using a single current pulse.
Product development efforts in flash memory devices have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times, reducing cell dimensions, and optimizing dielectric materials used in memory cells. One important dielectric material for fabrication of the flash memory device is an Oxide-Nitride-Oxide (ONO) stack. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO stack. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom oxide layer and become trapped and stored in the nitride layer.
The ONO stack can be utilized in memory cells capable of storing two independent bits in separate locations within the memory cell, such as Advanced Micro Devices' (AMD) MirrorBit™ memory cells, to achieve high-density flash memory devices. The MirrorBit™ memory cell includes a bit line, a word line, and an ONO stack, which function together to determine the location of a bit stored in memory. In a typical memory cell array utilizing memory cells capable of storing two independent data bits in separate locations within each memory cell, an ONO stack is formed and patterned over a substrate, which includes columns of bit lines. Word lines are formed over the patterned ONO stack and memory cells are formed at each intersection of a word line and a bit line, such that adjacent memory cells share the same word line.
In each memory cell discussed above, a right and a left bit can be stored in separate storage locations situated on the right and left sides, respectively, of the memory cell. The right and left bits are stored as electrical charges, which, as discussed above, are stored in the nitride layer of the ONO stack in each memory cell. However, since adjacent memory cells share a common ONO stack, electrical charge might undesirably travel in the nitride layer of the ONO stack between, for example, a right storage location in one memory cell and a left storage location in an adjacent memory cell. As a result, after a number of programming cycles, charge loss can occur in the memory cell, which can degrade the reliability of the memory cell. In current practice, the charge loss can occur after, for example, approximately 10,000 to 100,000 programming cycles.
Thus, there is a need in the art for a more reliable memory cell.
SUMMARY
The present invention is directed to structure and method for reducing charge loss in a memory cell. The present invention addresses and resolves the need in the an for a more reliable memory cell.
According to one exemplary embodiment, a structure comprises a first bit line and a second bit line. The structure further comprises a first memory cell situated over the first bit line, where the first memory cell comprises a first ONO stack segment, and where the first ONO stack segment is situated between the first bit line and a word line. The structure further comprises a second memory cell situated over the second bit line, where the second memory cell comprises a second ONO stack segment, where the second ONO stack segment is situated between the second bit line and the word line, and where the first ONO stack segment is separated from the second ONO stack segment by a gap.


REFERENCES:
patent: 6030871 (2000-02-01), Eitan
patent: 2002/0196665 (2002-12-01), Kim

Affiliated with

Also associated with

Rating

Structure and method for reducing charge loss in a memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Structure and method for reducing charge loss in a memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Structure and method for reducing charge loss in a memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3186637