Structure and method for manufacturing a series read only memory

Details Structure and method for manufacturing a series read only memory Structure and method for manufacturing a series read only memory

1990-10-30

1991-11-19

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 2312, 357 2314, 307448, H01L 2934

Patent

active

050670018

ABSTRACT:
Disclosed is a device and method for manufacturing a mask read only memory (ROM) using a spacing film and NAND logic to attain high integration density. Side wall layers are separated between connection regions and reference regions with gate oxide layers formed on a surface of the substrate and gate electrode formed over side walls of the side wall layers placed between each of the gate oxide layers and adjacent memory cells. Channel regions having a first conductivity type of ion are formed under memory cells adjacent to the connection region and oxide layers of selected memory cells. Channel regions exhibiting a second conductivity type of ion are formed under the oxide layers of the non-selected memory cells and the side wall layers.

REFERENCES:
patent: 4142176 (1979-02-01), Dozier
patent: 4380863 (1983-04-01), Rao
patent: 4385308 (1983-05-01), Uchida
Dockerty, "Semiconductor Hole Fabricating," Aug. 1983, IBM Technical Disclosure Bulletin, vol. 26, No. 3A, pp. 1091-1093.

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