Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-10-02
2007-10-02
Baumeister, B. William (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S623000, C257S347000, C257SE29259, C257SE29262, C438S157000, C438S283000
Reexamination Certificate
active
11300896
ABSTRACT:
In a method of forming semiconductor device, a semiconductor fin is formed on a semiconductor-on-insulator substrate. A gate dielectric is formed over at least a portion of the semiconductor fin. A first gate electrode material is formed over the gate dielectric and a second gate electrode material is formed over the first gate electrode material. The second gate electrode material is planarized and then etched selectively with respect to first gate electrode material. The first gate electrode material can then be etched.
REFERENCES:
patent: 4933298 (1990-06-01), Hasegawa
patent: 4946799 (1990-08-01), Blake et al.
patent: 5115289 (1992-05-01), Hisamoto et al.
patent: 5317175 (1994-05-01), Throngnumchai
patent: 5317178 (1994-05-01), Wu
patent: 5464783 (1995-11-01), Kim et al.
patent: 5607865 (1997-03-01), Choi et al.
patent: 5814895 (1998-09-01), Hirayama
patent: 5998852 (1999-12-01), Berry et al.
patent: 6114725 (2000-09-01), Furukawa et al.
patent: 6157061 (2000-12-01), Kawata
patent: 6222234 (2001-04-01), Imai
patent: 6252284 (2001-06-01), Muller et al.
patent: 6300182 (2001-10-01), Yu
patent: 6342410 (2002-01-01), Yu
patent: 6344392 (2002-02-01), Liaw
patent: 6380024 (2002-04-01), Liaw
patent: 6387739 (2002-05-01), Smith, III
patent: 6391695 (2002-05-01), Yu
patent: 6391782 (2002-05-01), Yu
patent: 6391796 (2002-05-01), Akiyama et al.
patent: 6411725 (2002-06-01), Rhoads
patent: 6413802 (2002-07-01), Hu et al.
patent: 6432829 (2002-08-01), Muller et al.
patent: 6451656 (2002-09-01), Yu et al.
patent: 6475869 (2002-11-01), Yu
patent: 6475890 (2002-11-01), Yu
patent: 6476437 (2002-11-01), Liaw
patent: 6492212 (2002-12-01), Ieong et al.
patent: 6514808 (2003-02-01), Samavedam et al.
patent: 6521949 (2003-02-01), Assaderaghi et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6534807 (2003-03-01), Mandelman et al.
patent: 6573549 (2003-06-01), Deng et al.
patent: 6596599 (2003-07-01), Guo
patent: 6605514 (2003-08-01), Tabery et al.
patent: 6610576 (2003-08-01), Nowak
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6617210 (2003-09-01), Chau et al.
patent: 6635909 (2003-10-01), Clark et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 6657252 (2003-12-01), Fried et al.
patent: 6686231 (2004-02-01), Ahmed et al.
patent: 6706571 (2004-03-01), Yu et al.
patent: 6720231 (2004-04-01), Fried et al.
patent: 6768158 (2004-07-01), Lee et al.
patent: 6992354 (2006-01-01), Nowak et al.
patent: 2002/0011612 (2002-01-01), Hieda
patent: 2003/0011080 (2003-01-01), Deshpande et al.
patent: 2003/0042528 (2003-03-01), Forbes
patent: 2003/0057486 (2003-03-01), Gambino et al.
patent: 2003/0067017 (2003-04-01), Ieong et al.
patent: 2003/0102497 (2003-06-01), Fried et al.
patent: 2003/0111678 (2003-06-01), Colombo et al.
patent: 2003/0113970 (2003-06-01), Fried et al.
patent: 2003/0178670 (2003-09-01), Fried et al.
patent: 2003/0178677 (2003-09-01), Clark et al.
patent: 2004/0007715 (2004-01-01), Webb et al.
patent: 2004/0031979 (2004-02-01), Lochtefeld et al.
patent: 2004/0038464 (2004-02-01), Fried et al.
patent: 2004/0061178 (2004-04-01), Lin et al.
patent: 2004/0075122 (2004-04-01), Lin et al.
patent: 2004/0119100 (2004-06-01), Nowak et al.
patent: 2004/0145000 (2004-07-01), An et al.
patent: 2 617 642 (1989-01-01), None
patent: 02-015675 (1990-01-01), None
Solymar et al., “Electrical Properties of Materials,” 1998, Sixth Edition, pp. 152.
Auth, C.P., et al., “Scaling Theory for Cylindrical, Fully-Depleted, Surrounding-Gate MOSFET's,” IEEE Electron Device Letters, Feb. 1997, pp. 74-76, vol. 18, No. 2.
Celik, M., et al., “A 45 nm Gate Length High Performance SOI Transistor for 100nm CMOS Technology Applications,” Symposium on VLSI Technology Digest of Technical Papers, 2002, pp. 166-167.
Chau, R., et al., “A 50nm Depleted-Substrate CMOS Transistor (DST),” IEDM, 2001, pp. 621-624, IEEE.
Chau, R., et al., “Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and and Tri-gate”, (Invited Paper), Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials, Nagoya, 2002, pp. 68-69.
Chen, W., et al., “Suppression of the SOI Floating-Body Effects by Linked-Body Device Structure,” Symposium on VLSI Technology Digest of Technical Papers, 1996, pp. 92-93, IEEE.
Colinge, J.P., et al., “Silicon-On-Insulator ‘Gate-All-Around Device’”, IEDM, 1990, pp. 595-598, IEEE.
Fung, S.K.H., et al., Gate Length Scaling Accelerated to 30nm Regime Using Ultra-Thim Flim PD-SOI Technology, IEDM, 2001, pp. 629-632.
Geppert, L., “The Amazing Vanishing Transistor Act,” IEEE Spectrum, Oct. 2002, pp. 28-33.
Huang, X., et al., “Sub-50 nm P-Channel FinFET”, IEEE Transactions on Electron Devices, May 2001, pp. 880-886, vol. 48, No. 5.
Kranti, A., et al., “Design Guidelines of Vertical Surrounding Gate (VSG) MOSFETs for Future ULSI Circuit Applications,” IEEE, 2001, pp. 161-165.
Leobandung, E., et al., “Wire-channel and wrap-around-gate metal-oxide-semiconductor field-effect transistors with a significant reduction of short channel effects”, American Vacuum Society, Nov./Dec. 1997, pp. 2791-2794, J. Vac. Sci. Technol., vol. 15, No. 6.
Je, M., et al., “Quantized Conductance of a Gate-All-Around Silicon Quantum Wire Transistor,” Microprocesses and Nanotechnology Conference, 1998, pp. 150-151.
Nemati, F., et al., “A Novel Thyristor-Based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-Scale Memories,” IEDM, 1999, pp. 283-286.
Nitayama, A., et al., “Multi-Pillar Surrounding Gate Transistor (M-SGT) for Compact and High-Speed Circuits,” IEEE Transactions on Electron Devices, Mar. 1991, pp. 579-583, vol. 38, No. 3.
Oh, S.-H., et al., “Analytic Description of Short-Channel Effects in Fully-Depleted Double-Gate and Cylindrical, Surrounding-Gate MOSFETs,” IEEE Electron Device Letters, Sep. 2000, pp. 445-447, vol. 21, No. 9.
Sato, N., et al., “Hydrogen Annealed Silicon-On-Insulator,” Appl. Phys. Lett., Oct. 10, 1994, pp. 1924-1926, vol. 65, No. 15.
Shahidi, G.G., “SOI Technology for the GHz Era,” IBM J. Res. & Dev., Mar./May 2002, pp. 121-131, vol. 46, No. 2/3.
Tang, S.H., et al., “FinFET—A Quasi-Planar Double-Gate MOSFET,” IEEE International Solid-State Circuits Conference, 2001, pp. 118-119 & 437.
Wong, H.-S.P., “Beyond the Conventional Transistor,” IBM J. Res. & Dev., Mar./May 2002, pp. 133-167, vol. 46, No. 2/3.
Yamagata, K., et al., “Selective Growth of Si Crystals from the Agglomerated Si Seeds over Amorphous Substrates,” Appl. Phys. Lett., Nov. 23, 1992, pp. 2557-2559, vol. 61, No. 21.
Yang, F.-L., et al., “25 nm CMOS Omega FETs”, IEDM, Feb. 2002, pp. 255-258, IEEE.
Yang, F.-L., et al., “35nm CMOS FinFETs”, Symposium On VLSI Technology Digest of Technical Papers, 2002, pp. 104-105, IEEE.
Yang Fu-Liang
Yeo Yee-Chia
Baumeister B. William
Fulk Steven J.
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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