Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-10-18
1998-02-10
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438633, 438784, 438699, 257634, 257644, H01L 21316
Patent
active
057168903
ABSTRACT:
The present invention provides a structure and method of manufacturing an interlevel/intermetal dielectric layer for a semiconductor device. The method begins by forming a stepped pattern 16 on a semiconductor structure 12. A barrier layer 20 composed of silicon oxide is formed on the semiconductor substrate so as to cover the surface of the stepped pattern 16. A first insulating layer 22 composed of silicon oxide is then formed over the barrier layer 20. A high P (phosphorous) content silicon glass layer 24 preferably is formed over the first insulating layer 22. The high P content silicon glass layer 24 has a phosphorous concentration in a range of about 4 and 10 weight percent. Next, in an important step, a graded P content silicon glass layer 26 is formed over the high P content silicon glass layer 24. The graded P content silicon glass layer 26 has a phosphorous concentration in a range of about 0.1 and 4 weight percent. A capping layer 28 composed of first silicon oxide is formed over the graded P content silicon glass layer 26. The capping layer can be treated with an optional N.sub.2 or Ar plasma treatment. The capping layer 28 is then planarized using a chemical mechanically polishing process thereby removing a portion of the capping layer 28.
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Ackerman Stephen B.
Bowers Jr. Charles L.
Saile George O.
Stoffel William J.
Vanguard International Semiconductor Corporation
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