Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-01-20
2008-10-28
Quach, Tuan N. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S372000, C257SE27063
Reexamination Certificate
active
07442996
ABSTRACT:
Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p− substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.
REFERENCES:
patent: 5470766 (1995-11-01), Lien
patent: 5652456 (1997-07-01), Lien
patent: 5668755 (1997-09-01), Hidaka
patent: 5814866 (1998-09-01), Borland
patent: 5880014 (1999-03-01), Park et al.
patent: 5939757 (1999-08-01), Kim
patent: 6107672 (2000-08-01), Hirase
patent: 6114729 (2000-09-01), Park et al.
patent: 6249030 (2001-06-01), Lee
patent: 6258641 (2001-07-01), Wong et al.
patent: 6300209 (2001-10-01), Oh
patent: 6396109 (2002-05-01), Hutter et al.
patent: 6531363 (2003-03-01), Uchida
patent: 6593178 (2003-07-01), Lee
patent: 6664150 (2003-12-01), Clark, Jr. et al.
patent: 6664608 (2003-12-01), Burr
patent: 6727573 (2004-04-01), Mitani et al.
patent: 6767780 (2004-07-01), Sohn et al.
patent: 6855985 (2005-02-01), Williams et al.
patent: 6956266 (2005-10-01), Voldman et al.
patent: 6975015 (2005-12-01), Voldman et al.
patent: 2002/0084506 (2002-07-01), Voldman et al.
patent: 2003/0178622 (2003-09-01), Wei et al.
patent: 2004/0135141 (2004-07-01), Pequignot et al.
patent: 2004/0164354 (2004-08-01), Mergens et al.
patent: 0831518 (1998-03-01), None
patent: 05-267606 (1993-10-01), None
Voldman, et al., “The Influence of Deep Trench and Substrate Resistance on the Latchup Robustness in a BICMOS Silicon Germanium Technology,” Reliab. Phys. Symp. Proc. 42nd Annual, IEEE Int., Apr. 2004, pp. 135-142.
Voldman, et al., “Latchup in Merged Triple Well Structure,” Reliab. Phys. Symp. Proc. 43rd Annual, IEEE Int., Apr. 2005, pp. 129-136.
Voldman, et al, “The Influence of a Silicon Dioxide-Filled Trench Isolation Structure and Implanted Sub-Collector on Latchup Robustness,” Reliab. Phys. Symp. Proc. 43rd Annual, IEEE Int., Apr. 2005, pp. 112-120.
Collins David S.
Slinkman James A.
Voldman Steven H.
Canale Anthony
Gibb & Rahman, LLC
International Business Machines - Corporation
Quach Tuan N.
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