Structure and manufacturing method for DRAM capacitors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438397, 257309, 365149, H01L 2170, H01L 2700

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active

058917721

ABSTRACT:
A structure and manufacturing method for DRAM capacitors includes providing a semiconductor substrate with a MOS transistor having a gate and source/drain regions formed thereon. A first insulating layer covers the semiconductor substrate. A multi-layered stack, with at least one pair of an alternately deposited second insulating layer followed by a third insulating layer, is formed above the first insulating layer. An opening is formed through the multi-layered structure and the first insulating layer exposing the source/drain region. Then, a plurality of trenches are formed on the sidewalls of the opening. A second conducting layer is formed over the exposed surfaces of the aforementioned layers. A pattern is defined on the second conducting layer so as to form a lower electrode structure. A dielectric layer is formed over the lower electrode layer. A third conducting layer is formed over the dielectric layer, and a pattern is defined on the third conducting layer to form the upper electrode structure.

REFERENCES:
patent: 5434812 (1995-07-01), Tseng
patent: 5637523 (1997-06-01), Fazan et al.
patent: 5672534 (1997-09-01), Huang
patent: 5701264 (1997-12-01), Shrivastava et al.

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