Structural integrity enhancement of dielectric films

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Reexamination Certificate

active

06455365

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor fabrication processing and more particularly to a method for increasing the overall reliability of dielectric films used in semiconductor devices, such as dynamic random access memories (DRAMs).
BACKGROUND OF THE INVENTION
In the manufacturing of dynamic random access memories (DRAMs) the size of the memory cell is the main contributing factor to the density and overall size of the device. A manufacturer of DRAMs has motivation to increase the storage capability, while maintaining the smallest die size possible, as the smaller die size results in a lower cost per device. As mentioned, the main contributor to the size of a memory device is the amount of space required for each storage cell that makes up the storage array. In that regard, DRAM fabrication engineers have focused on storage cell structures, on materials to make the structures and on methods to fabricate the structures necessary to make a storage cell.
To save space, the capacitor of the storage cell must reduce in size and yet maintain adequate capacitance to retain a sufficient charge during DRAM operation. There are several approaches to the capacitor design, for example trench capacitors formed in the substrate of a wafer or a stacked capacitor formed above the wafer substrate, to name two. Regardless of the design chosen, there is a great incentive to minimize the physical size of the capacitor and yet maintain sufficient capacitance as mentioned previously. Two of the main contributors to capacitance are the surface area of the capacitor plates and the dielectric quality of the insulator separating the capacitor plates.
Major engineering efforts have gone into both of the areas. In regards to dielectric quality, thin film dielectrics having high dielectric constant characteristics have emerged as the dielectric of choice, as the thinnest film that can be placed between the capacitor plates that will prevent dielectric breakdown when a charge is present on the capacitor plates drastically increases capacitance. With increased capacitance, the overall size of the capacitor can be reduced. However, thin film dielectrics present some challenges in fabricating the complete storage cell structure, which includes a storage cell access transistor and a storage capacitor.
One of the thin dielectric films of choice is nitride (i.e., silicon nitride) as nitride possesses sufficient dielectric constant characteristics and can be deposited as a very thin layer (<100 Å). However a nitride film of this thickness must be conditioned is some manner to plug any pinholes in the film and thus maintain the dielectric integrity of the entire film. Therefore, new challenges to condition the thin film arise once a nitride film that is 50 Å or less in thickness is desired. The present invention presents methods to successfully address these new challenges, as will become apparent to those skilled in the art from the following disclosure.
SUMMARY OF THE INVENTION
The present invention teaches a method for reducing the diffusing of oxygen atoms through a dielectric film during a semiconductor fabrication process. This method uses a thin dielectric layer that is of such thickness that may allow oxygen atoms to diffuse completely through it. Then the thin dielectric layer is exposed to a wet oxidation during a rapid thermal oxidation step. The rapid thermal oxidation step is performed at a temperature and time duration which are sufficient to oxidize the thin dielectric layer to prevent the diffusion of a majority of oxygen atoms through it, and at the same time maintain the dielectric integrity or original dielectric characteristics of the thin film.
One implementation of the present invention is to utilize a nitride dielectric layer that is 50 Å or less in thickness for the intended use as a storage capacitor dielectric. The nitride dielectric layer is exposed to wet oxidation during a rapid thermal oxidation step. This rapid thermal oxidation step is performed at a temperature range and a time duration which are sufficient to oxidize the nitride dielectric layer to prevent the diffusion of a majority of oxygen atoms through the nitride dielectric layer and to maintain the nitride layer's dielectric integrity.
A second implementation of the present invention comprises as two stage RTP process that is sufficient to oxidize nitride dielectric layer, to prevent the diffusion of a majority of oxygen atoms through the nitride dielectric layer, to effectively fill the pinholes for leakage current reduction and to maintain the dielectric integrity throughout the film by first forming weak spots (first stage) and then healing them (second stage). If a given process does not use a reflowable material underneath the nitride layer then the first stage oxidation step could be eliminated and only the second stage oxidation step be implemented.
This method provides a way to effectively utilize a thin dielectric film layer that is 50 Å or less in thickness as a storage capacitor dielectric which will possess sufficient dielectric characteristics to hold a required charge. This method can be applied to other devices that would benefit from the use of a thin dielectric film, such as a floating gate device, that operates by storing a charge.


REFERENCES:
patent: 6037219 (2000-03-01), Lin et al.
Chang et al., ,,Rapid Thermal Oxidation of Thin Nitride/Oxide Stacked Layer, Appl. Phys. Lett., 54 (5), p 430-2 (1989).
Itoh et al., “Formation of High-Quality Oxide/Nitride Stacked Layers on Rugged Polysilicon Electrodes by Rapid Thermal Oxidation”, IEEE Transactions on Electron Devices, vol. 40 (6), p 1176-9 (1993).
Hwang et al., “Improved Reliability Characteristics of Submicrometer nMOSFET's with Oxynitride Gate Dielectric Prepared by Rapid Thermal Oxidation in N2O”, IEEE Electron.
Wolf and Tauber, Silicon processing for the VLSI Era, vol. 1 (Lattice Press, 1986. Chapters 7 and 8.

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