Stressed MOS device and method for its fabrication

Details Stressed MOS device and method for its fabrication Stressed MOS device and method for its fabrication

2005-11-07

2008-08-12

Lindsay, Jr., Walter L (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S301000, C257SE21561

Reexamination Certificate

active

07410859

ABSTRACT:
A stressed MOS device and a method for its fabrication are provided. The MOS device comprises a substrate having a surface, the substrate comprising a monocrystalline semiconductor material having a first lattice constant. A channel region is formed of the monocrystalline silicon material adjacent the surface. A stress inducing monocrystalline semiconductor material having a second lattice constant greater than the first lattice constant is grown under the channel region to exert a horizontal tensile stress on the channel region.

REFERENCES:
patent: 4925805 (1990-05-01), van Ommen et al.
patent: 2003/0057438 (2003-03-01), Yu et al.
patent: 2004/0150076 (2004-08-01), Ramdani et al.
patent: 2004/0151463 (2004-08-01), Talin et al.
patent: 2004/0227186 (2004-11-01), Saito et al.
patent: 2006/0001018 (2006-01-01), Chow et al.
patent: 2007/0026593 (2007-02-01), Jawarani et al.
patent: 2007/0072380 (2007-03-01), Wirbeleit et al.

Affiliated with

Also associated with

Rating

Stressed MOS device and method for its fabrication does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stressed MOS device and method for its fabrication, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stressed MOS device and method for its fabrication will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4012074