Stress buffered bond pad and method of making

Details Stress buffered bond pad and method of making Stress buffered bond pad and method of making

1998-06-22

1999-08-24

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257755, 257765, 257390, 257391, 257211, H01L 2348

Patent

active

059428007

ABSTRACT:
A method for forming a chess-board patterned bond pad structure with stress buffered characteristics and the bond pad structure formed are disclosed. In one method, a multiplicity of field oxide regions are first formed in the surface of a silicon substrate. A conductive layer such as polycide is then deposited and formed on the substrate to form a stepped surface with a metal layer subsequently deposited on top of the conductive layer to form a bond pad. The stepped structure reproduced on the metal layer serves to distribute bonding stresses during a wire bonding process such that bond pad lift-off defects are substantially eliminated. In another method, the conductive layer is first formed into conductive gates with insulating sidewalls formed subsequently. Similarly stepped surface on a metal layer can be obtained to realize the stress buffered characteristics of the novel method.

REFERENCES:
patent: 4984061 (1991-01-01), Matsumoto
patent: 5598028 (1997-01-01), Losavio et al.
patent: 5686762 (1997-11-01), Langley

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