Strapping via for interconnecting integrated circuit structures

Details Strapping via for interconnecting integrated circuit structures Strapping via for interconnecting integrated circuit structures

1997-07-22

2002-02-26

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S255000, C438S392000, C438S554000, C438S618000, C148SDIG002, C148SDIG003, C257S754000

Reexamination Certificate

active

06350645

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process and structure for interconnecting different layers in an integrated circuit such as a static random access memory (SRAM).
2. Description of Related Art
SRAMs (static random access memories) are well known circuits which contain arrays of SRAM cells.
FIG. 1
shows a circuit diagram of a four-transistor SRAM cell
100
. SRAM cell
100
contains N channel transistors
110
and
120
and pull-up resistors
114
and
124
that control the voltages on nodes
112
and
122
. Transistors
110
and
120
are cross-coupled and connect respective nodes
112
and
122
to a reference voltage Vss. In particular, transistor
110
has its gate coupled to node
122
which is the drain of transistor
120
, and transistor
120
has its gate coupled to node
112
which is the drain of transistor
110
. The sources of transistors
110
and
120
are connected to reference voltage Vss. Pull-up resistors
114
and
124
connect respective nodes
112
and
122
to a supply voltage Vcc.
The voltage on node
112
has two stable states which correspond to binary values of a bit. In both states, the voltage on node
122
is complementary to the voltage on node
112
. When the voltage on node
112
is high (near supply voltage Vcc), transistor
120
conducts and pulls the voltage at node
122
low (near reference voltage Vss) which shuts off transistor
110
and allows pull-up device
114
to keep the voltage at node
112
high. When the voltage on node
112
is low, transistor
120
is off and pull-up device
124
pulls the voltage at node
122
high which turns on transistor
110
and keeps the voltage at node
112
low.
Pass transistors
116
and
126
connect respective nodes
112
and
122
to respective bit lines
118
and
128
. Bit lines
118
and
128
couple to a column of SRAM cells a column decoder, a write circuit, and a sense amplifier (not shown). A word line
150
couples to a row decoder (not shown) and to the gates of pass transistors in a row of SRAM cells. To access SRAM cell
100
, the row decoder applies a voltage to word line
150
which turns on pass transistors
116
and
126
and connects nodes
112
and
122
to bit lines
118
and
128
respectively. Once accessed, the sense amplifier reads SRAM cell
100
by sensing the voltages on nodes
112
and
122
, or the write circuit writes to SRAM cell
100
by driving complementary voltages on bit lines
118
and
128
.
Although SRAM cells are well known, semiconductor structures which form the SRAM cells vary in shape and construction. Typically, the layout of the features within SRAM cells and design rules which control the size of the features limit the minimum SRAM cell size. Generally, a layout and process are desired to provide a compact SRAM cell that can be formed within a small area of a semiconductor substrate because a compact SRAM cell typically reduces manufacturing costs per circuit by increasing the number of SRAM cells which can be formed on a wafer. Accordingly, compact interconnect structures for SRAM cells are desired.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the invention, a triple-poly process forms three layers of polysilicon during fabrication of a static random access memory (SRAM). The triple-poly process permits a compact layout for four-transistor SRAM cells. In one layout, the first polysilicon layer forms gate regions for the transistors in the SRAM cells. A second polysilicon layer forms cross-couple interconnects and fixed voltage lines. A third polysilicon layer forms pull-up resistors. Spreading the structures of an SRAM cell over more layers reduces the area of the SRAM cells.
To compensate for the reduced dimensions of cell areas, pull-up resistors, which are formed from the third polysilicon layer, extend across the boundaries of the cell areas. Further, the pull-up resistors are not required to follow the symmetry of underlying structures. Accordingly, the pull-up resistors can be longer than would be possible if the resistors were symmetric and confined to the boundaries of a cell area.
In accordance with another aspect of the invention, strapping vias which cross-couple the gate of a first transistor in an SRAM cell and the drain of a second transistor in the SRAM cell further reduce cell area. The strapping via connects a substrate region which forms the drain to an adjacent polysilicon region which forms the gate. Typically, the strapping via is a portion of a structure such as a pull-up resistor which requires a connection to the underlying drain and gate. To create the strapping via, an opening is formed through overlying layers to expose adjacent portions of the gate region and the substrate region, and then a layer of material such as polysilicon is deposited in the opening to form a strap in contact with the gate region and the substrate region. During subsequent thermal processes, diffusion of dopants from the gate and substrate regions into polysilicon which forms the strapping via can provide a good electrical connection. Thus, the strapping via provides a compact structure which simultaneously accomplishes the goals of connecting a pull-up resistor to a node in an SRAM cell and cross-coupling transistors in the SRAM cell.


REFERENCES:
patent: 5198683 (1993-03-01), Sivan
patent: 5212399 (1993-05-01), Manning
patent: 5238861 (1993-08-01), Morin et al.
patent: 5320973 (1994-06-01), Kobayashi
patent: 5320975 (1994-06-01), Cederbaum et al.
patent: 5359266 (1994-10-01), DeJong
patent: 5459688 (1995-10-01), Pfiester et al.
patent: 5943598 (1999-08-01), Lin
patent: WO92/020242 (1992-06-01), None
S.M. Sze, VLSI Technology, 2nd edition, pp 308-313, 1988.

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