Strained transistor architecture and method

Details Strained transistor architecture and method Strained transistor architecture and method

2006-05-09

2006-05-09

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S475000, C438S630000

Reexamination Certificate

active

07041543

ABSTRACT:
Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is NMOS devices using a highly tensile post-salicide silicon nitride capping layer on the source and drain regions. The stress from this capping layer is uniaxially transferred to the NMOS channel through the source-drain regions to create tensile strain in NMOS channel.

REFERENCES:
patent: 6147014 (2000-11-01), Lyding et al.
patent: 6444533 (2002-09-01), Lyding et al.
patent: 6888204 (2005-05-01), Lyding et al.
patent: 2005/0170104 (2005-08-01), Jung et al.
Peter Singer, “New Materials and Designs to Improve Transistor Performance”, Apr. 1, 2004, Semiconductor International.
Ghani et al, “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”, IEEE, © 2003.
Bhadri N. Varadarajan, “Tensile Silicon Nitride—P1264 NESL”, C & F Study, Aug. 21, 2003.

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