Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-31
2004-06-29
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S514000
Reexamination Certificate
active
06756276
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to fabrication of metal oxide semiconductor field effect transistors (MOSFETs), and more particularly, to MOSFETs that achieve improved carrier mobility through the incorporation of strained silicon.
2. Related Technology
MOSFETs are a common component of integrated circuits (ICs).
FIG. 1
shows a conventional MOSFET device. The MOSFET is fabricated on a semiconductor substrate
10
within an active area bounded by shallow trench isolations
12
that electrically isolate the active areas of the MOSFET from other IC components fabricated on the substrate
10
.
The MOSFET is comprised of a gate electrode
14
that is separated from a channel region
16
in the substrate
10
by a thin gate insulator
18
such as silicon oxide or oxide-nitride-oxide (ONO). To minimize the resistance of the gate
14
, the gate
14
is typically formed of a doped semiconductor material such as polysilicon.
The source and drain of the MOSFET are provided as deep source and drain regions
20
formed on opposing sides of the gate
14
. Source and drain silicides
22
are formed on the source and drain regions
20
and are comprised of a compound that combines the substrate semiconductor material and a metal such as cobalt (Co) or nickel (Ni) to reduce contact resistance to the source and drain regions
20
. The deep source and drain regions
20
are formed deeply enough to extend beyond the depth to which the source and drain silicides
22
are formed. The deep source and drain regions
20
are implanted subsequent to the formation of spacers
30
around the gate and gate insulator which serve as an implantation mask to define the lateral position of the deep source and drain regions
20
relative to the channel region
16
beneath the gate.
The gate
14
likewise has a silicide
24
formed on its upper surface. The gate structure comprising a polysilicon material and an overlying silicide is sometimes referred to as a polycide gate.
The source and drain of the MOSFET further comprise shallow source and drain extensions
26
. As dimensions of the MOSFET are reduced, short channel effects resulting from the small distance between the source and drain cause degradation of MOSFET performance. The use of shallow source and drain extensions
26
rather than deep source and drain regions near the ends of the channel
18
helps to reduce short channel effects. The source and drain extensions are implanted prior to the formation of the gate spacers
30
and the gate
14
acts as an implantation mask to define the lateral position of the source and drain extensions
26
relative to the channel region
18
. Diffusion during subsequent annealing causes the source and drain extensions
26
to extend slightly beneath the gate
14
.
Implanted adjacent to the shallow source and drain extensions
26
are so-called “halo” regions
28
. The combination of shallow source and drain extensions and halo regions is sometimes referred to as a double-implanted shallow source and drain extension. The halo regions
28
are implanted with a dopant that is opposite in conductivity type to the dopant of the source and drain extensions
26
. For example, when the source and drain extensions are implanted with an n-type dopant such as arsenic (As) or phosphorous (P), the halo regions are implanted with a p-type dopant such as boron (B). The halo regions help to suppress a short channel effect known as punchthrough, which occurs when the channel length of the device is sufficiently short that the depletion regions at the ends of the source and drain extensions to overlap, thus effectively merging the two depletion regions. Any increase in reverse-bias drain voltage beyond that required to establish punchthrough lowers the potential energy barrier for majority carriers in the source, resulting in a punchthrough current between the source and drain that must be suppressed for proper device operation. The presence of the halo regions
28
shortens the depletion regions at the ends of the source and drain extensions
26
and thus allows the fabrication of MOSFETs having shorter channel regions while avoiding punchthrough. The halo regions
28
may be formed by low energy implantation of dopant at an angle to the substrate so as to ensure that the halo regions extend beyond the ends of the source and drain extensions
26
.
One recent area of investigation for improvement of the conventional MOSFET is the incorporation of “strained” silicon in the semiconductor substrate. Strained silicon is a form of silicon in which a tensile strain is applied to the silicon lattice as a result of the difference in the dimensionalities of the silicon lattice and the lattice of the underlying material on which it is formed. In the illustrated case, the silicon germanium lattice is more widely spaced than a pure silicon lattice, with the spacing becoming wider as the percentage of germanium increases. Because the silicon lattice aligns with the larger silicon germanium lattice during formation, a tensile strain is imparted to the silicon layer. In essence, the silicon atoms are pulled apart from one another. Relaxed silicon has a conductive band that contains six equal valence bands. The application of tensile strain to the silicon causes four of the six valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons meet with less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. Consequently, carrier mobility is dramatically increased in strained silicon compared to relaxed silicon, providing a potential increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
FIG. 2
shows an example of an N-type MOSFET (NMOS) incorporating strained silicon and formed in accordance with the conventional processing used to form the MOSFET of FIG.
1
. The MOSFET of
FIG. 2
differs from the MOSFET of
FIG. 1
in that it is formed on a silicon germanium substrate
34
over which is formed an epitaxial layer of strained silicon
36
. The upper portions of the channel region
18
and the source and drain regions
20
are formed in the strained silicon layer
36
. The thickness of the strained silicon layer
36
is less than the depth of the shallow source and drain extensions
26
.
The arsenic dopant of the NMOS shallow source and drain extensions
26
and deep source and drain regions
20
diffuses at a greater rate in silicon germanium than in silicon, and as a result, during processing such as rapid thermal annealing (RTA) to activate the implanted dopants, the growth of the shallow source and drain extensions
26
and the deep source and drain regions
20
is greater in the silicon germanium substrate
34
than in the strained silicon layer
36
. As a result, the shallow source and drain extensions
26
develop distorted outgrowths
38
that effectively shorten the channel length in the silicon germanium layer
34
and increase the risk of punchthrough and other short channel effects.
Therefore the n-type strained silicon MOSFET formed in accordance with the conventional processing used to form an NMOS on a relaxed silicon substrate suffers from degraded short channel effect resistance compared to the conventional MOSFET.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide the enhancements of strained silicon in a conventional NMOS device without significantly degrading the resistance of the device to short channel effects
Goo Jung-Suk
Wang Haihong
Xiang Qi
Advanced Micro Devices , Inc.
Lindsay Jr. Walter L.
Niebling John F.
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