Strained-silicon channel CMOS with sacrificial shallow...

Details Strained-silicon channel CMOS with sacrificial shallow... Strained-silicon channel CMOS with sacrificial shallow...

2003-01-17

2004-11-30

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S359000, C438S663000

Reexamination Certificate

active

06825086

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to integrated circuit fabrication and, more particularly, to a strained-silicon (Si) channel CMOS device that has shallow trench isolation (STI) regions formed with an oxide liner.
2. Description of the Related Art
In the process of trenching for a STI region, damage can occur in the exposed silicon-containing layers. A STI liner oxidation process is typically carried out at 800-1000 degrees C., growing a 100-300 Å thick layer of SiO2. This oxidation process cures the damaged Si, rounding the STI top and bottom corners and reducing the stress at trench corners. The Si curing induced by this STI liner oxidation step can reduce the device junction leakage up to several orders of magnitude.
For strained-Si channel complementary metal gate over oxide over silicon (CMOS) field effect transistor (FET) processes, the thin layer of strained-Si is deposited on a layer of relaxed silicon germanium (SiGe). Then, the above-described oxidation process can lead to other problems. The exposure of SiGe, in the trenching process and the oxidation ambient environment as the liner oxide is grown, generally results in Ge precipitation into the SiO2 matrix. This Ge precipitation degrades the device performance with respect to junction leakage and device reliability.
It would be advantageous if an oxidation curing process could be performed after a STI trenching, when SiGe layers are etching.
It would be advantageous if a procedure could be developed that prevented the precipitation of Ge, from a SiGe layer, in the oxidation curing of a STI trench.
It would be advantageous if the above-mentioned procedure could be performed using primarily conventional procedures.
SUMMARY OF THE INVENTION
This present invention solves the above-mentioned Ge precipitation problem by growing a sacrificial (temporary) liner oxide, and removing it, after curing the damaged Si in an STI trench. As mentioned above, the curing removes damaged Si, rounds the STI top/bottom corners, and reduces the stress at trench corners. In some aspects, a very thin liner oxide (<100 Å) is regrown as the barrier to the CVD oxide deposited in the STI trench.
Accordingly, a method is provided for forming a sacrificial STI oxide liner in a strained-silicon channel CMOS device using a relaxed-SiGe layer. The method comprises: forming a Si substrate; and, forming a relaxed-SiGe layer overlying the Si substrate. In some aspects the Si substrate is a bulk Si substrate. In other aspects, the relaxed-SiGe layer is formed over an interposing buried oxide (BOX) layer to form a SiGe on insulator (SGOI) substrate.
The method further comprises: forming a strained-Si layer overlying the relaxed-SiGe layer; forming a silicon oxide layer overlying the strained-Si layer; forming a silicon nitride layer overlying the silicon oxide layer; etching the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface; forming a sacrificial oxide liner on the STI trench surface; in response to forming the sacrificial oxide liner, rounding and reducing stress at the STI trench corners; removing the sacrificial oxide liner; and, filling the STI trench with silicon oxide.
Typically, the sacrificial oxide liner on the STI trench surface has a thickness in the range of 20 to 300 Å, formed through a thermal oxidation process at a temperature in the range of 300 to 1100 degrees C. The sacrificial oxide liner is moved using either a hydrofluoric (HF) vapor or an HF solution.
In some aspects of the method, the SiGe layer is formed as a SiGe layer having a top surface with a Ge content in the range between 10 and 50%. The SiGe layer can either have a variably graded Ge content, or a constant content throughout the SiGe layer thickness. When the Si substrate is bulk Si, the SiGe layer has a thickness in the range of 0.1 micron to 7 microns. When, a SGOI substrate is used, the SiGe layer has a thickness in the range of 0.005 to 0.5 microns, and the STI trench bottom is formed in the BOX underlying the relaxed-SiGe layer.
Some aspects of the method include further steps comprising: following the removal of the sacrificial oxide liner, forming a permanent oxide liner on the STI trench surface, typically with a thickness of less than 100 Å. Then, filling the STI trench with silicon oxide includes depositing silicon oxide in the STI trench overlying the permanent oxide liner.
Additional details of the above-described method and a strained-Si channel CMOS device STI oxide region are described below.


REFERENCES:
patent: 6194285 (2001-02-01), Lin et al.
patent: 6464780 (2002-10-01), Mantl et al.
patent: 6600170 (2003-07-01), Xiang
patent: 6677192 (2004-01-01), Fitzgerald
patent: 6723661 (2004-04-01), Fitzergald

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