Strained channel on insulator device

Details Strained channel on insulator device Strained channel on insulator device

2005-05-31

2005-05-31

Wojcichowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S340000, C257S348000, C257S616000, C257S618000

Reexamination Certificate

active

06900502

ABSTRACT:
A semiconductor device10includes a substrate12(e.g., a silicon substrate) with an insulating layer14(e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer16(e.g., SiGe) is disposed on the insulating layer14and a second semiconducting material layer18(e.g., Si) is disposed on the first semiconducting material layer16. The first and second semiconducting material layers16and18preferably have different lattice constants such that the first semiconducting material layer16is compressive and the second semiconducting material layer is tensile18.

REFERENCES:
patent: 4314269 (1982-02-01), Fujiki
patent: 4497683 (1985-02-01), Celler et al.
patent: 4631803 (1986-12-01), Hunter et al.
patent: 4946799 (1990-08-01), Blake et al.
patent: 5447884 (1995-09-01), Fahey et al.
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5479033 (1995-12-01), Baca et al.
patent: 5534713 (1996-07-01), Ismail et al.
patent: 5629544 (1997-05-01), Voldman et al.
patent: 5714777 (1998-02-01), Ismail et al.
patent: 5763315 (1998-06-01), Benedict et al.
patent: 5811857 (1998-09-01), Assaderaghi et al.
patent: 6008095 (1999-12-01), Gardner et al.
patent: 6015993 (2000-01-01), Voldman et al.
patent: 6046487 (2000-04-01), Benedict et al.
patent: 6059895 (2000-05-01), Chu et al.
patent: 6111267 (2000-08-01), Fischer et al.
patent: 6222234 (2001-04-01), Imai
patent: 6232163 (2001-05-01), Voldman et al.
patent: 6258664 (2001-07-01), Reinberg
patent: 6291321 (2001-09-01), Fitzgerald
patent: 6294834 (2001-09-01), Yeh et al.
patent: 6339232 (2002-01-01), Takagi
patent: 6358791 (2002-03-01), Hsu et al.
patent: 6387739 (2002-05-01), Smith, III
patent: 6407406 (2002-06-01), Tezuka
patent: 6413802 (2002-07-01), Hu et al.
patent: 6414355 (2002-07-01), An et al.
patent: 6429061 (2002-08-01), Rim
patent: 6448114 (2002-09-01), An et al.
patent: 6475838 (2002-11-01), Bryant et al.
patent: 6489664 (2002-12-01), Re et al.
patent: 6524905 (2003-02-01), Yamamichi et al.
patent: 6555839 (2003-04-01), Fitzgerald
patent: 6558998 (2003-05-01), Belleville et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6600170 (2003-07-01), Xiang
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6653700 (2003-11-01), Chau et al.
patent: 2002/0076899 (2002-06-01), Skotnicki et al.
patent: 2002/0153549 (2002-10-01), Laibowitz et al.
patent: 2002/0190284 (2002-12-01), Murthy et al.
patent: 2003/0001219 (2003-01-01), Chau et al.
patent: 2003/0030091 (2003-02-01), Bulsara et al.
patent: 2003/0080386 (2003-05-01), Ker et al.
patent: 2004/0026765 (2004-02-01), Currie et al.
patent: 0 683 552 (1995-11-01), None
patent: 0 828 296 (1998-03-01), None
patent: WO 03/017336 (2003-02-01), None
Leitz, C.W. et al., “Channel Engineering of SiGe-Based Heterostructures for High Mobility MOSFETs,” Materials Research Society Symposium Proceedings, vol. 686, (2002), pp. 113-118.
Leitz, C.W., et al., “Hole mobility enhancements in strained Si/Si1-xGexp-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si1-xGex(x<y) virtual substrates,” Applied Physics Letters, vol.79, No. 25, (2001) pp. 4246-4246, Dec. 17, 2001.
Liu, K.C., et al., “A Novel Sidewall Strained-Si Channel nMOSFET,” IEDM, (1999) pp. 63-66.
Huang, X., et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Shahidi, G.G., “SOI Technology for the GHz Era,” IBM J. Res. & Dev., vol. 46, No. 2/3, Mar./May 2002, pp. 121-131.
Shimzu, A., et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Perfomance Enhancement,” IEDM 2001, pp. 433-436.
Wong, H.-S.P., “Beyond the Conventional Transistor,” IBM J. Res. & Dev., vol. 46, No. 2/3, Mar./May 2002, pp. 133-167.
Yang, F.L., et al., “25nm CMOS Omega FETs,” IEDM 2002, pp. 255-258.
Yang, F.L., et al, “35nm CMOS FinFETs,” 2002 Symposium on VLSI Technology Digest of Technical Papers, 2002, pp. 104-105.
Thompson, S., et al., “A 90 nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 Layers of Cu Interconnects, Low k ILD, and 1 um2SRAM Cell,” IEDM, pp. 61-64.
Welser, J., et al., “NMOS and PMOS Transistors Fabricated in Strained Silicon/Relaxed Silicon-Germanium Structures,” IEDM 1992, pp. 1000-1002.
Wang, L.K., et al., “On-Chip Decoupling Capacitor Design to Reduce Switching-Noise-Induced Instability in CMOS/SOI VLSI,” Proceedings of the 1995 IEEE International SOI Conference, Oct. 1995, pp. 100-101.
Yeoh, J.C., et al., “MOS Gated Si:SiGe Quantum Wells Formed by Anodic Oxidation,” Semicond. Sci. Technol. (1998), vol. 13, pp. 1442-1445, IOP Publishing Ltd., UK.
Cavassilas, N., et al., “Capacitance-Voltage Characteristics of Metal-Oxide-Strained Semiconductor Si/SiGe Heterostructures,” Nanotech 2002, vol. 1, pp. 600-603.
Blaauw, D., et al., “Gate Oxide and Subthreshold Leakage Characterization, Analysis and Optimization,” date unknown.
“Future Gate Stack,” International Sematech, 2001 Annual Report.
Chang, L., et al., “Reduction of Direct-Tunneling Gate Leakage Current in Double-Gate and Ultra-Thin Body MOSFETs,” 2001 IEEE, Berkeley, CA.
Chang, L., et al., “Direct-Tunneling Gate Leakage Current in Double-Gate and Ultrathin Body MOSFETs,” 2002 IEEE, vol. 49, No. 12, Dec. 2002.
Ismail, K, et al., “Electron Transport Properties of Si/SiGe Heterostructures: Measurements and Device Implications,” Applied Physics Letter, vol. 63, No. 5, (Aug. 2, 1993), pp. 660-662.
Nayak, D.K., et al., “Enhancement-Mode Quantum-Well GexSi1-xPMOS,” IEEE Electron Device Letters, vol. 12, No. 4, (Apr. 1991), pp. 154-156.
Gámiz, F., et al., “Strained-Si/SiGe-on-Insulator Inversion Layers: The Role of Strained-Si Layer Thickness of Electron Mobility,” Applied Physics Letter, vol. 80, No. 22, (Jun. 3, 2002), pp. 4160-4162.
Gámiz, F., et al., “Electron Transport in Strained Si Inversion Layers Grown on SiGe-on-insulator Substrates,” Journal of Applied Physics, vol. 92, No. 1, (Jul. 2002), pp. 288-295.
Mizuno, T., et al., “Novel SOI p-Channel MOSFETs With Higher Strain in Si Channel Using Double SiGe Heterostructures,” IEEE Transactions on Electron Devices, vol. 49, No. 1, (Jan. 2002), pp. 7-14.
Tezuka, T., et al., “High-Performance Strained Si-on-Insulator MOSFETs by Novel Fabrication Processes Utilizing Ge-Condensation Technique,” Symposium On VLSI Technology Digest of Technical Papers, (2002), pp. 96-97.
Jurczak, M., et al., “Silicon-on-Nothing (SON)—an Innovative Process for Advanced CMOS,” IEEE Transactions on Electron Devices, vol. 47, No. 11, (Nov. 2000), pp. 2179-2187.
Jurczak, M., et al., “SON (Silicon on Nothing)—A New Device Architechture for the ULSI Era,” Symposium on VLSI Technology Digest of Technical Papers, (1999), pp. 29-30.
Maiti, C.K., et al., “Film Growth and Material Parameters,” Application of Silicon-Germanium Heterostructure, Institute of Physics Publishing, Ch. 2 (2001) pp. 32-42.
Tiwari, S., et al., “Hole Mobility Improvement in Silicon-on-Insulator and Bulk Silicon Transistors Using Local Strain,” International Electron Device Meeting, (1997), pp. 939-941.
Ootsuka, F., et al., “A Highly Dense, High-Performance 130nm Node CMOS Technology for Large Scale System-on-a-Chip Applications,” International Electron Device Meeting, (2000), pp. 575-578.
Matthews, J.W., et al., “Defects in Epitaxial Multilayers—I. Misfit Dislocations,” Journal of Crystal Growth, vol. 27, (1974), pp. 118-125.
Matthews, J.W., et al., “Defects in Epitaxial Multilayers -II. Dislocation Pile-Ups, Threading Dislocations, Slip Lines and Cracks”, Journal of Crystal Growth, vol. 29, (1975), pp. 273-280.
Matthews, J.W., et al., “Defects in Epitaxial Multilayers—III. Prepa

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