Store stream prefetching in a microprocessor

Details Store stream prefetching in a microprocessor Store stream prefetching in a microprocessor

2005-02-10

2008-05-27

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S154000, C711S213000

Reexamination Certificate

active

07380066

ABSTRACT:
In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2Mcontiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.

REFERENCES:
patent: 5276848 (1994-01-01), Gallagher et al.
patent: 5958040 (1999-09-01), Jouppi
patent: 5983306 (1999-11-01), Corrigan et al.
patent: 6085291 (2000-07-01), Hicks et al.
patent: 6317811 (2001-11-01), Deshpande et al.
patent: 6460115 (2002-10-01), Kahle et al.
patent: 6574712 (2003-06-01), Kahle et al.
patent: 6578130 (2003-06-01), Barrick et al.
patent: 6651245 (2003-11-01), Damron et al.
patent: 6785772 (2004-08-01), Venkumahanti et al.
patent: 6981099 (2005-12-01), Paulraj et al.
patent: 7032076 (2006-04-01), Sprangle et al.
patent: 7177985 (2007-02-01), Diefendorff
patent: 2003/0088863 (2003-05-01), Tirumalai et al.
patent: 2004/0022094 (2004-02-01), Radhakrishnan et al.
patent: 2006/0095677 (2006-05-01), Hakura et al.
“Cache Organization”. ECEN 2120 Lecture Notes, University of Colorado at Boulder. 1999. pp. 1-6 http://web.archive.org/web/19991103235721/http://ece-www.colorado.edu/˜ecen2120/Manual/caches/cache.html.

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