Storage reading apparatus

Details Storage reading apparatus Storage reading apparatus

1995-05-03

1996-11-05

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365196, 36523008, 365233, G11C 700, G11C 800

Patent

active

055724680

ABSTRACT:
After a row address and a column address are supplied to a dynamic RAM in response to a row address strobe signal and a column address strobe signal, respectively, a high impedance state is maintained for column address access time period after the fall timing of the column address strobe signal, thereafter data is outputted to a data bus, and the high impedance state of the data bus is quickly resumed after the rise timing of the column address strobe signal. If different column addresses of RAM at the same row address are successively read, data are read and outputted to the data bus in response to a change only in the column address strobe signal, and thereafter, even after the high impedance state of the data bus is quickly resumed, a data value is held by the data bus until the dynamic RAM outputs the data.

REFERENCES:
patent: 5260904 (1993-11-01), Miyawaki et al.
patent: 5302867 (1994-04-01), Ahn
patent: 5430688 (1995-07-01), Takasugi

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