Storage node of DRAM cell

Details Storage node of DRAM cell Storage node of DRAM cell

2000-11-08

2004-02-24

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S309000, C361S321400

Reexamination Certificate

active

06696722

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for fabricating a DRAM cell capacitor, and more particularly to a method for fabricating a storage node thereof.
BACKGROUND OF THE INVENTION
In a dynamic random access memory (DRAM) device, the cell capacitance which is closely related to the product quality, may require a higher value than in a normal cell, for example, a 25 tF/cell. It is required that the value be higher.
Since the design rule becomes smaller as the cell density increases, a practical process margin, for example, an overlap margin between a storage node and contact plug is reduced. Accordingly, the height of the storage node is increased to obtain great capacitance in a small area.
FIG. 1
shows a structure of a storage node
10
of a conventional DRAM cell capacitor and
FIG. 2
shows an associated problem which arises due to the misalignment of storage node
10
of the conventional DRAM cell capacitor.
Referring to
FIG. 1
the structure for a storage node
10
of conventional
1
G DRAM and
256
M DRAM products is illustrated. Two insulating layers
2
and
6
are formed on a semiconductor substrate (not shown). Two bit line patterns
4
a
and
4
b
are formed in the insulating layers
2
and
6
. A storage node contact hole
8
is formed to expose a portion of the semiconductor substrate by penetrating the insulating layers
2
and
6
between the bit line patterns
4
a
and
4
b
. Storage node
10
is formed on the insulating layers
2
and
6
including the contact hole
8
.
In an exemplary 0.34 pitch cell the size ‘A’ of the contact hole
8
is about 100~130 nm and the top size ‘B’ of the storage node
10
is about 160 nm. As a result an overlap margin of the storage node
10
to the contact hole
8
is about 15~30 nm/side. The height ‘H’ of the storage node
10
may be formed with a thickness of about 10,000 Å to receive the desired cell capacitance.
It takes a considerable time to deposit undoped polysilicon, which is generally used to form the storage node
10
, due to above reasons. If the storage node
10
is misaligned, as shown in
FIG. 2
, an under-cut portion
12
is formed by over-etching. Subsequently, the falling-down of the storage node
10
may occur during a subsequent cleaning process.
SUMMARY OF THE INVENTION
The present invention addresses and overcomes the above-mentioned deficiencies of the prior art It is therefore an object of the invention to provide a method for fabricating a DRAM cell capacitor which can reduce the thickness of a polysilicon to form a storage node with the height of the storage node being maintained. In other words, the cell capacitance is maintained.
It is another object of the invention to provide a method for fabricating a DRAM cell capacitor which can minimize the total etch amount of a polysilicon layer for forming a storage node and prevent falling-down thereof generated by over-etching, a subsequent cleaning process, etc., despite the misalignment thereof.
According to these objects of this invention, the method includes forming a first insulating layer on a semiconductor substrate; forming a conductive layer pattern for forming bit lines on the first insulating layer; forming a second insulating layer to cover up the first insulating layer and bit line patterns; etching the second and first insulating layers of a region between bit line patterns to form a storage node contact hole; forming sequentially a first conductive layer, material layer, and second conductive layer on the second insulating layer including the contact hole, the material layer having an etching selectivity with respect to the first conductive layer; patterning the second conductive layer and material layer by using a mask for forming a storage node; forming a third conductive layer on the first conductive layer including the second conductive layer pattern and material layer pattern; and forming a poly-spacer on both side-walls of the second conductive layer pattern and material layer pattern by etching back the third conductive layer and first conductive layer thereunder to expose a surface of the second insulating layer, so that a storage node is formed by the first, second, and third conductive layers.
In a preferred embodiment of the present invention, the first, second, and third conductive layer are made of polysilicon.
In a preferred embodiment of the present invention, the first, second, and third conductive layer have a thickness of about 100~10,000 Å. Preferably, the first conductive layer has a thickness of about 500~5,000 Å. Preferably, the second conductive layer has a thickness range of about 500~5,000 Å and the third conductive layer has a thickness of about 100~3,000 Å.
In a preferred embodiment of the present invention, the material layer is either an insulating layer or conductive layer.
In a preferred embodiment of the present invention, the insulating layer is an oxide layer deposited relatively fast by either an APCVD (atmospheric pressure chemical vapor deposition) method or LPCVD (low pressure chemical vapor deposition) method.
In a preferred embodiment of the present invention, the conductive layer is made of one selected from a group consisting of W, TiN, W silicide, and Ti silicide.
In a preferred embodiment of the present invention, the material layer has a thickness of about 2,000~30,000 Å.
Referring to
FIG. 3D
, insulating layers formed on a semiconductor substrate are etched to form a storage node contact hole. A first conductive layer, material layer, and second conductive layer are sequentially formed wherein the material layer has an etching selectivity with respect to the first conductive layer. The second conductive layer and material layer are patterned by a mask for forming the storage node. A third conductive layer is formed on the first conductive layer including the second conductive layer pattern and material layer pattern. The third conductive layer and the first conductive layer thereunder are etched back to form a poly-spacer. A storage node is formed by the fist, second, and third conductive layer, thereby decreasing the thickness of a storage node polysilicon layer with the height of an existing storage node, that is, cell capacitance maintained and reducing the process throughput as well as minimizing the total etch amount of the polysilicon layer for forming a storage node during formation thereof. In addition the present invention reduces the over-etch amount of the polysilicon layer, and prevents the falling-down of a storage node generated by an over-etch and a subsequent cleaning process despite the misalignment of the storage node.


REFERENCES:
patent: 5825609 (1998-10-01), Andricacos et al.
patent: 5-283613 (1993-10-01), None
patent: 6-151755 (1994-05-01), None

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