Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1999-03-17
2002-01-01
Heckler, Thomas M. (Department: 2787)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C710S061000
Reexamination Certificate
active
06336190
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a storage apparatus having a storage control section and a plurality of clock synchronized storage elements and, more particularly, relates to a storage apparatus with a clocked parallel transfer system which tolerates changes in the operating frequency.
BACKGROUND OF THE INVENTION
In a storage apparatus for use in a computer system operating at high speeds, it is possible that the signal transferring time from the storage control section to the farthest storage element exceeds one operating cycle. As a result, the storage control section is unable to accept the information signals delivered from the plurality of storage elements, each thereof having different transferring times, all at the same timing. In such cases, when asynchronous type storage elements are used, circuits for delaying the clocks are usually provided to compensate for the storage elements being at different distances. Since the clock signals are supplied to these delay circuits, information signals from the farthest storage element and the nearest storage element are accepted by flip-flops at the same time.
SUMMARY OF THE INVENTION
When storage elements of a clock-synchronized type are used, the storage elements operate in synchronism with the clock. This can cause a problem with write operations into a certain logical unit of a storage element group which must be made at the same timing. To solve this problem, the transfer times are equalized by making all of the distances from the storage control section to each of the storage elements the same. Specifically, this can be achieved by ensuring that the required distances from the storage control section to the storage elements are equal to the distance from the storage control section to the farthest storage element. When full-synchronous transfer under such conditions is attempted, an increase in the transfer delay caused by making the required distances equal to the farthest storage element results. Accordingly, it is difficult to secure the operation margin when parameters such as the set-up time are defined on the basis of the timing of the clocks input to the storage elements, especially if general-purpose storage elements are used. Accordingly, it becomes difficult to hold the operating frequency. Therefore, the memory throughput greatly drops and the processor performance also decreases.
A primary object of the present invention is to provide a storage apparatus with a clocked parallel transfer system, in which the timing of the clocks is matched to the delay in the transferred information signals, in both writing and reading operations, whereby the problems related to delay and ensuring the operation margin required for high-speed operation are overcome.
Another object of the invention is to provide a storage apparatus with a clocked parallel transfer system capable of flexibly setting the timing for achieving transfer time matching among the storage elements to thereby suppress the need to change the number of required cycles for reading or writing, which occurs when the operating frequency is decreased below the regular frequency.
A further object of the invention is to provide a storage apparatus capable of efficiently suppressing the occurrence of delays in the distribution system and fluctuations in the delay, which occur when a clock tree is formed in the distribution system for generating return clocks for accepting the read data.
According to the invention, the storage apparatus has a storage control section and a plurality of storage elements of the clock-synchronized type. When information signals are transferred from the storage control section to the plurality of storage elements, signals are transferred that have a specific relationship with the clock for delivering the information signals to the plurality of storage elements. Such signals are, for example, parallel transfer clock signals that are associated with the information signals and function as the clock for the storage elements under timing constraints related to the delay in the transfer of the information signals to the storage elements. And, when the information signals are transferred from the plurality of storage elements to the storage control section, signals are transferred having a specific relationship with the clock for the storage element. Such signals are, for example, return parallel transfer clock signals associated with the information signals and used as the clock for the storage control section to accept the information signals under timing constraints related to the delay in the transfer of the information signals to the storage control section.
Further, the invention includes storage element phase-locked loop circuits (PLL circuits) to which the storage elements are connected. Signals are transferred from the storage control section that are associated with the information signals and that are used as the reference signals for the storage element PLL circuits to thereby match the phase of the clocks for the storage elements with the timing for accepting the information signals.
The storage element PLL circuits function to adjust the phase of its output such that the reference input and the feedback input are put in the same phase. The adjustment is made to ensure that the number of cycles required for the reading or writing operation dose not change even when the apparatus is operated at a lower operating frequency than the regular operating frequency. The PLL circuit functions without the need for switching means for adapting to the change in the operating frequency, and the feedback amount in the PLL circuit may be made great so that the relative time difference between the information signal and the source clock signal becomes one cycle to thereby match the relative time difference with the accepting timing of the information signals.
Further, the invention includes a storage control section PLL circuit that is connected to receive a signal transferred from the storage elements that is associated with the information signals as the reference signal for the PLL circuit. The storage control section PLL circuit matches the phase of the clocks for accepting the information signals from the storage elements with the timing for accepting the information signals. For example, according to a preferred embodiment of the invention, after a signal such as the return parallel transfer clock is returned to the PLL circuit, the output of the PLL circuit is supplied, through a clock distribution tree, as the clocks for a group of flip-flops to accept the information signals and one of the clocks is used as the feedback signal for the storage control section PLL circuit, so that fluctuations in the matching of the timing of the return parallel transfer clocks are suppressed.
REFERENCES:
patent: 4989223 (1991-01-01), Katayose et al.
patent: 5548620 (1996-08-01), Rogers
patent: 5706474 (1998-01-01), Takeuchi et al.
patent: 5933623 (1999-08-01), Umemura et al.
patent: 8-180678 (1996-07-01), None
patent: 9-180432 (1997-07-01), None
Isobe Tadaaki
Yamagishi Toshihiro
Heckler Thomas M.
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
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