Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-12-29
2002-12-31
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S664000
Reexamination Certificate
active
06501166
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to microelectronic packages and, more particularly, to a structure and process that stitches together correlated power planes in a microelectronic package.
BACKGROUND OF THE INVENTION
A modern microelectronic package typically includes a microelectronic die (i.e., a silicon chip) mounted to a substrate with an epoxy-based material. The substrate can be metal, a laminated epoxy glass, or a ceramic plate, and is usually comprised of multiple conductive layers (e.g., power, ground, and signal planes). The microelectronic die may be mounted to the substrate in a variety of ways. In the commonly used flip-chip device, for example, the microelectronic die is mounted face-down to a wiring substrate so that conductive terminals in the microelectronic die (usually in the form of solder balls) are directly physically and electrically connected to a wiring pattern on the substrate.
As microprocessor speeds continue to increase, the assembly of the microelectronic package is having an increasingly greater impact on both the power delivery performance and the I/O (i.e., signal) performance of the system. For example, as clock speeds increase to several hundred megahertz or higher, conventional packaging technology may no longer be satisfactory to accommodate signal transmission requirements.
One method for improving I/O performance has been to utilize a dual referenced stripline stackup. This stackup consists of a metal trace sandwiched between two reference planes which are set at the power rails and have opposite polarities (e.g., a Vcc power plane and a Vss ground plane). The advantage of this stackup is that it ensures return path integrity from the microelectronic die to the motherboard across both rails. However, because power delivery performance in high-speed devices is primarily governed by the amount of noise on the power and ground rails, there has been a demand for improved circuit design and packaging techniques where the signal redistribution processes can be more rapidly and reliably carried out with less electrical noise.
REFERENCES:
patent: 5033970 (1991-07-01), Buchoff
patent: 5413964 (1995-05-01), Massingill et al.
patent: 5625225 (1997-04-01), Huang et al.
patent: 5656547 (1997-08-01), Richards et al.
patent: 5789807 (1998-08-01), Correale, Jr.
patent: 5956575 (1999-09-01), Bertin et al.
patent: 6008534 (1999-12-01), Fulcher
patent: 6054758 (2000-04-01), Lamson
patent: 6075285 (2000-06-01), Taylor et al.
patent: 6087199 (2000-07-01), Pogge et al.
patent: 6145438 (2000-11-01), Berglund et al.
patent: 6326235 (2001-12-01), Glenn
Burton Edward A.
Ong Seng Hooi
Wood Dustin
Blakely , Sokoloff, Taylor & Zafman LLP
Clark Sheila V.
Intel Corporation
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