Stitched micro-via to enhance adhesion and mechanical strength

Details Stitched micro-via to enhance adhesion and mechanical strength Stitched micro-via to enhance adhesion and mechanical strength

2007-06-12

2007-06-12

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S625000, C438S650000, C438S654000, C257S774000, C257S775000

Reexamination Certificate

active

10670975

ABSTRACT:
A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material. The integrated circuit packaging substrate also includes a via for interconnecting the first layer of conductive material and the second layer of conductive material having a base that includes an interfacial adhesion material to stitch the base of the via to a layer of circuitry.

REFERENCES:
patent: 6495200 (2002-12-01), Chan et al.
patent: 2005/0181598 (2005-08-01), Kailasam
patent: 2005/0215046 (2005-09-01), Cohen et al.

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