Stitch and select implementation in twin MONOS array

Details Stitch and select implementation in twin MONOS array Stitch and select implementation in twin MONOS array

2002-03-26

2004-07-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S258000, C438S259000, C438S260000, C438S267000, C438S287000, C365S185020, C365S185180, C365S185270, C365S185280, C365S185290

Reexamination Certificate

active

06759290

ABSTRACT:

BACKGROUND OF THE INVENTION
1) Field of Invention
The invention relates to stitching (strapping) methods of forming high-density Metal/polysilicon Oxide Nitride Oxide Silicon (MONOS) memory arrays with reduced bit line resistance, reduced control gate resistance and reduced word gate resistance using three-level metal lines, resulting in high density MONOS memory arrays with high performance
2) Description of Prior Art and Background
Twin MONOS structures were introduced in the U.S. Pat. No. 6,255,166, and U.S. patent applications Ser. No. 09/861,489 and 09/595,059 by Seiki Ogura et al. and also various array fabrication methods of the twin MONOS memory array were introduced in U.S. Pat. Nos. 6,177,318 and 6,248,633 B1 and U.S. patent application Ser. No. 09/994,084 filed on Nov. 21, 2001.
The twin ballistic MONOS memory cell, illustrated in
FIG. 1A
, may be arranged into a bit diffusion array as follows: each memory cell contains two nitride regions
031
which comprise storage elements for one word gate
040
, and half a source diffusion and half a bit diffusion (
003
). The diffusion junctions are shared by two adjacent storage elements. Control gates can be defined separately (
042
) or shared together (
043
) over the same diffusion (
003
). The control gate is electrically isolated from the underlying diffusion junctions. Diffusions are shared between cells and run in parallel to the sidewall control gates (
042
), and perpendicular to the word line (
041
). The diffusion lines become bit lines.
In a conventional MOSFET memory, a transistor structure consisting of one polysilicon gate between source and drain diffusions is used and word gate polysilicon line and diffusion bit lines are orthogonally placed. When the memory array gets large, the bit line (BL) and word gate line (WG) become long. The word line resistance due to the series of word gates is high in large memory devices. In order to reduce word line resistance, it is necessary to connect the word line periodically to a metal line that runs in parallel to the poly word lines. This is referred to as a “stitched” or “strapped” word line. Also the bit diffusion line can be sub-arrayed and the bit line can be “stitched” by a conductive metal line. In a typical memory, each polysilicon word line is stitched to a metal word line which runs on top of each poly word line, and each diffusion line, which runs orthogonally to the word lines is stitched by another layer of metal line.
However, in the high-density twin MONOS cell shown in
FIG. 1A
, the transistor consists of three gates between source and drain diffusions. Three resistive layers of control gate and word gate and bit diffusion may need to be stitched to reduce resistance and to achieve the target performance. For higher density, the polysilicon control gate lines and diffusion bit lines may run in parallel to and on top of each other. If the cell is metal-pitch limited and requires stitching, that means that two additional layers of metal lines have to run on top of and contact to the two resistive layers. This is a layout and process challenge, as it is not possible to stitch two resistive layers to two respective metal layers when the set of the composite four lines are running on top of each other within the minimum metal pitch.
SUMMARY OF THE INVENTION
In the memory cell described hereinabove, however, another third resistive layer is added and stitched by the third level metal. Then a clever three-dimensional solution makes it possible to stitch three resistive layers by three metal lines.
An objective of the present invention is to provide a new method of stitching between high resistance lines and low resistance metal lines in a memory cell having three types of high resistance lines.
Another objective of the present invention is to provide a new method of stitching such that the three high resistance lines can be stitched by three low resistance metal lines within a cell size that is limited by the minimum metal pitch.
Yet another objective of the present invention is to provide a method of forming the stitch contact areas for the high resistance line.
A further objective of the present invention is to provide a method of stitching three high resistance lines to low resistance metal lines while providing bit line select transistors.
A still further objective of the present invention is to provide a method of stitching three high resistance lines to low resistance metal lines while providing bit line and control gate select transistors.
In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches.
When the memory becomes too large, the total capacitance of the bit line also becomes too large and the RC time constraint becomes too large for a specific application speed. Therefore, the bit line needs to be subdivided into several sections. Each section is selected by placing a select transistor at each end of the subdivided section. Thus, the total bit line capacitance is reduced to the sum of the global metal line capacitance and the selected section of devices. Also the above stitching invention is extended to the case of placing select transistors on the bit line. Also another stitching method for the deviated array structure provided in U.S. patent application Ser. No. 09/994,084 is also presented using a similar method.
FIG. 2
provides a conceptual illustration of a memory cell array having control gate lines
142
and bit lines
103
running in parallel to each other, and the word gate line
140
perpendicular to both the control gate and bit lines. Word gate polysilicon lines are stitched to metal. The diffusion bit line is further divided into a sub-array by a bit line select transistor
196
, which connects to a main bit line. The control gate polysilicon line is also divided into a sub-array by a control gate line select transistor
195
, which connects to a main control gate.
The first embodiment of the invention provides a stitching method of three resistive layers to three conductive layers where two resistive layers (
003
,
042
) run on top of, and in parallel to each other, and the third resistive layer (
040
) runs orthogonally to the first two resistive layers (FIG.
3
). The cell width and height allows for one conductive metal in both the vertical and horizontal directions. Each resistive layer is periodically contacted (stitched) by a respective upper conductive layer to reduce the total resistive layer resistance. In order to reduce resistance, the middle resistive layer
2
(
042
) is periodically connected to the conductive layer
061
(M
1
), which is above it. In order to make a connection between the bottom resistive layer
1
(
003
) and the uppermost conductive layer M
3
(
081
), the second resistive layer
2
(
042
) is cut and separated in order to expose the bottom resistive layer
1
(
003
). Then a contact/via stack is built up from the bottom resistive layer
1
(
003
) to the top conductive layer
3
(M
3
)
081
. The two ends of the second resistive layer
2
(
042
) are connected together by contacting to the second conductive layer M
2
(
071
). This second conductive layer M
2
(
071
) wire bypasses the contact/via stack by using the open space of the adjacent cell. This bypass path will hereafter be referred to as a “loop”. Since this bypass loop of second conductive layer M
2
(
071
) blocks contact to the bottom resistive layer
1
(
061
), the stitch is placed on every other set of composite lines. The unstitched lines may be stitched at another location, a short or far distance away. Thus by utilizing one extra conductive metal layer, two resistive layers can be stitched to two conductive layers, when all four layers run in parallel to and on top of one another. The extra second conductive layer M
2
(
071
) is used o

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