Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2008-09-22
2010-12-14
Richards, N Drew (Department: 2895)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S435000, C438S400000, C438S424000, C257SE21540
Reexamination Certificate
active
07851328
ABSTRACT:
A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.
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patent: 2009/0053874 (2009-02-01), Dubois et al.
Yiming Li et al., “Strained CMOS Device With Shallow-Trench-Isolation Stress Buffer Layers”, IEEE Transactions on Electron Devices, vol. 55, No. 4, Apr. 2008, 0018-9383, pp. 1085-1089.
Masafuni Miyamoto et al., “Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics”, IEEE Transactions on Electron Devices, Vole 51, No. 3, Mar. 2004, 0018-9393/04, pp. 440-443.
Lee Tze-Liang
Liang Mong-Song
Liao Ming-Han
Yeh Ling-Yen
Diallo Mamadou
Haynes and Boone LLP
Richards N Drew
Taiwan Semiconductor Manufacturing Company , Ltd.
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