Stepped gate configuration for non-volatile memory

Details Stepped gate configuration for non-volatile memory Stepped gate configuration for non-volatile memory

2007-09-04

2007-09-04

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE29309

Reexamination Certificate

active

11257637

ABSTRACT:
A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.

REFERENCES:
patent: 5930634 (1999-07-01), Hause et al.
patent: 6406945 (2002-06-01), Lee et al.
patent: 6706599 (2004-03-01), Sadd et al.
patent: 6709934 (2004-03-01), Lee et al.

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