Step drain and source junction formation

Details Step drain and source junction formation Step drain and source junction formation

1999-02-22

2001-05-01

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S482000, C438S306000

Reexamination Certificate

active

06225176

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present invention relates to transistors with ultra-shallow source/drain extensions and to transistors with a step source/drain junction.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETs). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions (SDE) help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. These effects result in very leaky transistor and also degrade the robustness of the transistor to random process variations. The use of shallow source and drain extensions and, hence, controlling short-channel effects are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form deep source/drain contact junctions and shallow source/drain extensions. According to the conventional process, the source / drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or ion-implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions, as well as, to partially form the deep drain and source regions.
After the drain and source extensions are formed, silicon dioxide or silicon nitride spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain contact regions. The deep source/drain contact regions are used for silicidation purpose. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide or silicon nitride spacer.
Other conventional processes can utilize a single ion-implantation technique to form a uniform-depth source and drain region. The source and drain region is produced by a single ion implantation followed by a high temperature annealing process. However, it is very difficult to balance the different requirements for shallow extensions and deep contact regions.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source and drain extensions have become more difficult to manufacture. Formation of ultra-shallow source and drain extensions is critical to the fabrication of ULSI MOSFETs. For example, smaller transistors should have ultra-shallow source and drain extensions (less than 30 or 40 nanometer (nm) junction depth). Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Due to the so-called “channeling effect” conventional ion-implantation results in a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion-implantation and diffusion-doping techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate can cause the dopant to more easily diffuse (the so-called “Transient Enhanced Diffusion” effect, or TED). The diffusion often extends the source and drain extension vertically into the bulk semiconductor substrate.
Conventional dual-depth source and drain regions (e.g., deep source or drain region for silicide formation and shallow source/drain extension for controlling short-channel effects) can be disadvantageous. Dual-depth source and drain regions require that the design of the source/drain structure be balanced to minimize source/drain series resistance and to reduce short-channeling effects. As transistor dimensions continue to be reduced, the depth of deep S/D contact regions remains almost the same but the depth of shallow S/D extensions must be reduced. The increasing difference between the two depths makes transistor design more difficult. Making the source and drain extensions too short increases short-channeling effects; and making the source and drain extensions too long increases source/drain series resistance. Increased source and drain series resistance degrades transistor current drive and speed.
Thus, there is a need for a method of manufacturing source and drain junctions and their extensions that does not utilize a conventional double implant process. Further still, there is a need for transistors that do not have conventional deep source/drain regions and shallow source and drain extensions. Even further still, there is a need for an efficient method of manufacturing source and drain extensions that reduces design constraints posed by source/drain series resistance and short-channeling performance.
SUMMARY OF THE INVENTION
The present invention relates to a method of manufacturing an integrated circuit that includes forming at least a portion of a gate structure on a top surface of a silicon substrate, providing a first pre-amorphization implant, doping the substrate for drain and source extensions, and providing first spacers. The pre-amorphization implant creates a first amorphous region near the top surface of the substrate. The first spacers abut the gate structure. The method further includes providing a second pre-amorphization implant, doping the substrate to form intermediate source and drain regions, providing a second spacer, and providing a third dopant pre-amorphization implant. The second pre-amorphization implant creates a second amorphization region in the substrate. The second spacers abut the first spacers, and the third pre-amorphization implant creates a third amorphous region in the substrate. The method even further includes doping the substrate to form deep source and drain regions.
The present invention further relates to an ultra-large scale integrated circuit including a plurality of field effect transistors. The transistors have step source and drain junctions. The step source and drain junctions include a shallow source/drain extension, an intermediate extension region, and a deep source/drain junctions region. The intermediate extension region is shallower than the deep source/drain region and deeper than the shallow source/drain extension.
The present invention even further relates to a step source/drain region for a field effect transistor associated with an ultra-large scale integrated circuit. The step source/drain region is manufactured by a method comprising forming at least a portion of a gate structure on a top surface of a substrate, providing a first amorphization implant, doping the substrate for a shallow source/drain extension, providing first spacers, providing a second amorphization implant, doping the substrate for an intermediate region, providing second spacers, providing a third amorphization implant, doping the substrate for a deep source/drain region, and thermally annealing the substrate. The first amorphization implant creates a first amorphous semiconductor region near the top surface of the substrate, and the second amorphization region creates an intermediate amorphous semiconductor region in the substrate. The third amorphization implant creates a deep amorphous region in the semiconductor substrate.


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