Static information storage and retrieval – Read/write circuit – Precharge
Patent
1984-03-23
1986-09-16
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Precharge
365230, G11C 700
Patent
active
046126317
ABSTRACT:
A static type memory circuit has a plurality of memory cells arranged in a matrix form, a plurality of word lines and a plurality of pairs of bit lines, each of the word lines being coupled to memory cells on a corresponding row, each pair of the bit lines being commonly coupled to memory cells on a corresponding column, a sense amplifier circuit coupled to the bit lines, a row decoder for energizing one of the word lines in response to row address data, a transition detecting circuit for generating an output signal when the row address data is changed, a control signal generator for causing the sense amplifier circuit to be active in response to the output signal from the transition detecting circuit, and a precharge control circuit for controlling precharging of the bit lines in response to the output signal from the transition detecting circuit. The precharge control circuit precharges the bit line to "1" level potential when the sense amplifier circuit is rendered nonoperative in response to the output signal from the control signal generator, and stops the precharging operation in response to an output signal from the transition detecting circuit.
REFERENCES:
patent: 4405996 (1983-09-01), Stewart
patent: 4417328 (1983-11-01), Ochii
Stewart, "High-Density CMOS ROM Arrays", IEEE Journal of Solid-State Circuits vol. SC-12, No. 5, Oct. 1977.
Ochii et al., "An Ultralow Power 8K.times.8-Bit Full CMOS RAM with a Six-Transistor Cell", IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982.
Hardee et al., "A Fault-Tolerant 30 ns/375 mW 16K.times.1 NMOS Static RAM", IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981.
Popek Joseph A.
Tokyo Shibaura Denki Kabushiki Kaisha
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