Static semiconductor memory device using bipolar transistor

Details Static semiconductor memory device using bipolar transistor Static semiconductor memory device using bipolar transistor

1991-03-26

1993-06-01

Hille, Rolf

Static information storage and retrieval

Systems using particular element

Flip-flop

365179, 365190, G11C 1100, G11C 1134, G11C 700

Patent

active

052166309

ABSTRACT:
Disclosed is a bipolar SRAM including, in each memory cell, two NPN multiemitter transistors, with a base of one transistor being cross-connected to a collector of the other transistor. The respective collectors of these two multiemitter transistors in an arbitrary memory cell are connected to the same positive word line through a load. The first emitter of one of these two multiemitter transistors and the first emitter of the other transistor are connected to the same negative word line. Only when the positive word line corresponding to this negative word line is not selected, a data holding current flows to the negative word line from the first emitter of the transistor having a H level collector potential out of these two multiemitter transistors, and when the corresponding positive word line is selected, the negative word line is controlled not to allow the data holding current to flow. Furthermore, in a data writing, when the arbitrary memory cell is selected in order to reduce or eliminate a current flowing between a second emitter of one transistor of these two multiemitter transistors in the selected memory cell and a bit line connected thereto, the bit line is controlled.

REFERENCES:
patent: 4370736 (1983-01-01), Takahashi
patent: 4536860 (1985-08-01), Toyoda et al.
patent: 4601014 (1986-07-01), Kitano et al.
patent: 4604728 (1986-08-01), Okajima

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