Static random access memory with self timed bit line equalizatio

Details Static random access memory with self timed bit line equalizatio Static random access memory with self timed bit line equalizatio

1992-09-23

1994-10-11

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Precharge

36518911, 365204, 3652335, G11C 700

Patent

active

053553438

ABSTRACT:
A static memory array incorporates a bit line equalization transistor which is normally conductive so that the quiescent condition of the bit lines is to remain equalized. The equalization transistor is cut off for a predetermined period in response to detection of address transition. When a subsequent address transition occurs before the expiration of a predetermined period, the equalization transistor conducts again briefly, which conduction is followed by a period of nonconduction, for a predetermined duration, as long as another address transition is not detected. The equalization technique is applicable to local data lines as well as the bit lines of the memory.

REFERENCES:
patent: 4355377 (1982-10-01), Sud et al.
patent: 4658381 (1982-04-01), Reed et al.
patent: 4751680 (1988-06-01), Wang et al.
patent: 4878198 (1989-10-01), Roy
patent: 5036492 (1991-06-01), Runaldue

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