Static random access memory with modulated loads

Details Static random access memory with modulated loads Static random access memory with modulated loads

1989-04-27

1991-05-21

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Precharge

3652335, 365190, G11C 700

Patent

active

050181068

ABSTRACT:
A static random access memory (SRAM) comprises plural memory cells, a true-bit load and a complementary-bit load, a true-bit line and a complementary bit line, a sense amplifier and an address transition detector. The address transition detector is used to generate load pulses which switch off the loads just after either of the memory cells is selected. This speeds signal development during a read (or write) operation. Since provision is made for modulating the loads, they can be designed to permit larger-than-conventional currents to flow therethrough when maximally on. The loads are maximally on just after cell deselection to facilitate bit-line equalization between cell selections. Thus, the present invention provides for briefer inter-select periods, quicker reads upon cell selection, and, thus, a faster SRAM overall.

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Miyaji et al., "A 25ns 4Mb CMOS SRAM with Dynamic Bit Line Loads", ISSCC Digest of Tech. Papers, pp. 250-251, Feb. 1989.
Ohtani et al., "A 25ns 1Mb CMOS SRAM", ISSCC Digest of Technical Papers, pp. 264-265, Feb. 1987.

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