Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1982-01-28
1985-03-26
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365154, 365208, G11C 702
Patent
active
045077592
ABSTRACT:
In a MOS static RAM, data lines disposed in a memory array and common data lines to be coupled with the data lines through a data line selection circuit are supplied with bias voltages of a level lower than a power source voltage level through bias MOSFETs. Normally, where the stand-by period of the RAM is long, the bias voltages of the data lines and the common data lines are abnormally raised by the leakage currents or tailing currents of the bias MOSFETs. As a result, the data read-out speed of the RAM is lowered. Such abnormal potential increases of the data lines and the common data lines are prevented by connecting resistance elements of comparatively high resistances (such as made of polycrystalline silicon layers), between the respective data lines and common data lines and the ground point of the circuitry.
REFERENCES:
patent: 4272834 (1981-06-01), Noguchi et al.
Minato Osamu
Nakamura Hideaki
Tanimura Nobuyoshi
Uchibori Kiyofumi
Yasui Tokumasa
Hitachi Ltd
Hitachi Microcomputer Eng. Ltd.
Moffitt James W.
LandOfFree
Static memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Static memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Static memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1297952