Standard cell architecture and methods with variable design...

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

Reexamination Certificate

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C257S209000, C257S202000, C257S390000

Reexamination Certificate

active

07919792

ABSTRACT:
Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.

REFERENCES:
patent: 5268319 (1993-12-01), Harari
patent: 5279982 (1994-01-01), Crotti
patent: 6483136 (2002-11-01), Yoshida et al.
patent: 6483749 (2002-11-01), Choi et al.
patent: 7423310 (2008-09-01), Verhoeven
patent: 2003/0218920 (2003-11-01), Harari
Smith, M.J.S.; “Application-Specific Integrated Circuits”; Addison-Wesley VLSI Systems Series; Addison-Wesley Professional, (Jun. 20, 1997); Preface and Chapters 3.4-3.7, 5.1-5.4, 16, and 17; 74 pages. Also available at http://www.edacafe.com/books/ASIC/Book/.

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