Stacked via-stud with improved reliability in copper metallurgy

Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Physical stress responsive

Reexamination Certificate

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C438S050000, C438S622000, C438S623000, C438S638000

Reexamination Certificate

active

06972209

ABSTRACT:
A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

REFERENCES:
patent: 6417575 (2002-07-01), Harada et al.
patent: 6500750 (2002-12-01), Shroff et al.
patent: 2002/0001937 (2002-01-01), Kikuchi et al.
patent: 2003/0073302 (2003-04-01), Huibers

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