Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-22
2002-11-05
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S230000, C438S299000, C438S303000
Reexamination Certificate
active
06475853
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits having a decreased electrode-to-electrode distance and a manufacturing method thereof More particularly, but not exclusively, the invention relates to metal oxide semiconductor (MOS) transistors having the structure of narrowed gate electrode distance with the capability of eliminating the flow of leak current in a difffusion layer region between adjacent gate electrodes while increasing the operating speed of semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
Recent advances of micropatterning/microfabrication technology in the manufacture of semiconductor elements have enabled attainment of higher integration of an increased number of devices on one chip, while simultaneously supporting the fundamental technical basis for development of high-performance devices.
One approach to meet the needs is to further increase the integration density of currently available stacked metal oxide semiconductor (MOS) transistors. The term “stacked MOS transistors” as used herein may refer to those transistors with the device structure having a plurality of gate electrodes extending in parallel in the direction of the gate length. By way of example, since MOS transistors are such that the “nature” of transistors (gate current) is determinable depending upon the ratio of gate width to gate length, it is possible to generate a required gate current which increases in magnitude as the gate width increases. Forming a plurality of gate electrodes of a constant gate width in a diffusion layer region of limited dimension may enable formation of plural MOS transistors. More specifically, forming two parallel gate electrodes having the same gate width on a substrate surface corresponding to such difflusion layer region makes it possible to configure circuitry including a combination of two MOS transistors.
FIG. 1
illustrates a plan view of one typical prior known NAND circuit comprised of a p-type MOS (pMOS) transistors and a n-type MOS (nMOS) transistor. As shown, the NAND circuit includes an n-type diffusion layer
223
and a p-type diffuision layer
224
, above which gate electrodes
207
and
209
are formed. The diffusion layers
223
,
224
have electrodes
227
,
233
which are electrically connected together by metal lead patterns
235
. Due to the inherent structure of the cubit, the distance “A” between the gate electrodes of nMOS transistors is less than the distance “B” between the gate electrodes of nMOS transistors. The gate distance “A” may typically be 300 nanometers (nm). The planar structure of one NMOS transistor and its operation will be described with reference to FIG.
2
.
FIG. 2
is a plan view of one of the NMOS transistors constituting the NAND circuit with two gate electrodes formed insulatively overlying its diffusion layer. For example, the n-type diffusion layer
223
is formed in a semiconductor substrate, while parallel elongated gate electrodes
207
,
209
are formed over the diffusion layer
223
, wherein the gate electrode
207
is spaced apart from gate electrode
209
by a predefined distance that measures approximately 300 nm.
This prior art nMOS (part of the NAND circuit) transistor only generates a drain current when a voltage is applied to the electrodes
229
,
231
. In this case, a diffusion layer
223
a
may function as the source region, diffiision layer
223
b
serves as the drain region, and gate electrode
207
and
209
acts as the gate electrode, thus constituting a transistor which permits flow of a drain current from the source region
223
a
toward drain region
223
b
. Having two gate electrode (each gate width is thin) on one diffusion layer reduces the resistivity of the gate electrode. That increases the operation speed of the NMOS transistor.
FIGS. 3 through 6
which illustrate, in cross-section as taken on line A—A′ of
FIG. 2
, some of the major steps in the manufacture of the
FIG. 2
MOS transistor in a time sequential order.
First, as shown in
FIG. 3
, a semiconductor substrate
201
made typically of silicon is prepared, which is then doped by well-known ion implantation techniques with a p-type impurity to a concentration of 4×10
16
atoms per cubic centimeter (4E16 cm
−3
), forming a p-type well region
202
in the silicon substrate
201
. An element separation region
203
is formed by selective oxidation techniques; then, a gate oxide film
205
, of typically 6 nm thick, is formed by thermal oxidation on the p-well region
202
and element separation region
203
. Next, a non-doped polycrystaline silicon (poly-silicon) layer having a thickness of approximately 200 nm is formed by chemical vapor deposition (CVD) techniques. The resulting polysilicon layer is then etched forming electrodes
207
,
209
. At this time, these electrodes
207
,
209
are spaced apart from each other by about 300 nm, or more or less. Thereafter, an oxide film
206
is formed by low-pressure CVD (LPCVD) techniques on the gate oxide film
205
and electrodes
207
,
209
as well as element separation region
203
, to a thickness of for example 20 nm. Then, the p-well region
202
is doped by ion implantation with a chosen impurity such as arsenide through oxide film
206
at a dose of 3×10
14
atoms per square centimeter (3E14 l/cm
2
) while applying thereto an acceleration voltage of 60 kilo-electronvolts reV), and is then thermally annealed for activation of the dopant at 950° C. for 30 seconds to thereby form a “shallow” diffusion layer
211
(depth of 80 nm from the substrate surface) having “the extension structure ” of a sheet resistance of about 250 ohms per unit area (&OHgr;/□) as depicted in FIG.
3
.
Next, as shown in
FIG. 4
, a silicon nitride film
217
is deposited by LPCVD to a thickness of typically 100 nm, overlying the entire top surface of the semiconductor substrate. When this is done, a “gap” space defined between the neighboring electrodes
207
and
209
is not completely burred and defines a narrow recess portion or “grove” therebetween due to the fact that the distance between these electrodes
207
,
209
is 300 nm.
Thereafter, as shown in
FIG. 5
, the silicon nitride film
217
is subjected to anisotropic etching with the oxide film
206
being used as a stopper for removal of the entire upper 100 nm part of film
217
; the etching is terminated when the stopper film
206
is exposed at its top surface. At this time any silicon nitride deposited on the side walls of electrodes
207
and
209
still resides thereon, forming respective sidewall films
219
that are approximately 100 nm in maximal thickness. Next, with the sidewall films
219
used as a mask, the p-well region
202
is doped by ion implantation with a chosen impurity such as arsenide at an acceleration voltage of 65 keV to a dose of 5E15 (l/cm
2
), and is then annealed at 1050° C. for about 10 seconds, thus forming a “deep” diffusion layer
223
(its depth from the substrate surface is typically 150 nm, and its sheet resistance may be 60 (&OHgr;/□) as shown in FIG.
5
.
Here, for a decrease in surface resistivity of the electrodes
207
,
209
and diffusion layer
223
to speed up the operation of MOS transistors, one or more low-resistance silicides are formed near the electrodes by use of the salicide process, which will be explained as follows. First, the oxide film
206
is removed away using hydrofluoric acid solution with the sidewall films
219
used as a mask, exposing electrodes
207
,
209
and diffusion
223
. Then, titanium is entirely deposited by sputtering techniques on the exposed surface to a thickness of 30 nm or therearound, for formation of relatively high resistive silicides by a first-step annealing process at 750° C. for 30 seconds. During this process the titanium exhibits silicide reaction only with silicon residing in such exposed region while allowing titanium in the other part thereof to be kept unreacted. Such unreacted titanium is then selectively removed using a 1:1 mixed solution of sulf
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Picardat Kevin M.
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