Stacked polysilicon layer for boron penetration inhibition

Details Stacked polysilicon layer for boron penetration inhibition Stacked polysilicon layer for boron penetration inhibition

2002-04-08

2004-07-13

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S288000, C257S314000, C257S315000, C257S316000, C257S321000, C257S324000, C257S325000

Reexamination Certificate

active

06762454

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to semiconductor devices having a dielectric layer of a high-K material. In particular, the present invention relates to a stacked polysilicon layer for boron penetration inhibition.
BACKGROUND
A conventional field effect transistor (FET) is characterized by a vertical stack on a semiconductor substrate. The semiconductor substrate is doped with either n-type or p-type impurities to form an active region in the semiconductor substrate. The vertical stack includes a gate dielectric and a gate electrode. The gate dielectric of silicon dioxide (SiO
2
gate dielectric), for example, is formed on the semiconductor substrate. The gate electrode of polysilicon, for example, is formed on the gate dielectric. The gate electrode formed on the SiO
2
gate dielectric defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. The source and the drain are formed by dopant impurities introduced into the semiconductor substrate.
A pervasive trend in modem integrated circuit manufacture is to produce semiconductor devices, e.g., FETs, having feature sizes as small as possible. Many present processes employ features, such as gate electrodes and interconnects, which have less than a 0.18 &mgr;m critical dimension. As feature sizes continue to decrease, the size of the resulting semiconductor device, as well as the interconnect between semiconductor devices, also decreases. Fabrication of smaller semiconductor devices allows more semiconductor devices to be placed on a single monolithic semiconductor substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
As semiconductor device feature sizes decrease, the thickness of the SiO
2
gate dielectric decreases as well. This decrease in SiO
2
gate dielectric thickness is driven in part by the demands of overall device scaling. As gate electrode widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early semiconductor device scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. A maximum value of semiconductor device subthreshold current can be maintained while feature sizes shrink. Any or all of several quantities may be decreased by appropriate amounts including SiO
2
gate dielectric thickness, operating voltage, depletion width and junction depth, for example.
As a result of the continuing decrease in feature size, SiO
2
gate dielectric thickness has been reduced so much that SiO
2
layers of SiO
2
gate dielectrics are approaching thicknesses on the order of ten angstroms (Å) (1 nm). Unfortunately, a thin SiO
2
layer may break down when subjected to an electric field, particularly the SiO
2
layer less than 50 angstroms (Å) (5 nm) thick. It is probable that even for a relatively low gate voltage of 3V, electrons can pass through the thin SiO
2
layer by a quantum mechanical tunneling effect. In this manner, a leakage current may undesirably form between the gate electrode and the semiconductor substrate, adversely affecting the operability of the device. Leakage current increases exponentially for a two-fold decrease in SiO
2
layer thickness. The exponential increase in the SiO
2
layer leakage current significantly affects the operation of semiconductor devices, particularly with regard to standby power, dissipation, reliability and lifetime.
One proposed solution is to replace the SiO
2
material of the gate dielectric with a material having a dielectric constant value higher than SiO
2
(high-K dielectric material will be further explained below). Using a dielectric material having a high-K for the gate dielectric would allow a higher capacitance and an electric equivalent thickness of a thinner SiO
2
gate dielectric to be achieved while maintaining or increasing the physical thickness of the gate dielectric. For example, an aluminum oxide (Al
2
O
3
) layer with a K of 9.6 and a physical thickness of 62.5 angstroms (Å) (6.25 nm) is substantially electrically equivalent to a SiO
2
layer (K=3.9) having a physical thickness of 25 angstroms (Å) (2.5 nm). Thus, the gate dielectric of Al
2
O
3
would have an electrical equivalent thickness of 25 angstroms (Å) (2.5 nm) of SiO
2
, but have a physical thickness of 62.5 angstroms (Å) (6.25 nm). Therefore, the gate dielectric can be made electrically thin while being formed of a physically thicker layer. Alternatively, the electric equivalent thickness may be further reduced by reducing the physical thickness of the high-K dielectric material as should be understood by those skilled in the art. As a result, further device scaling can be achieved.
However, with the use of boron as a dopant for P+ gates, dopant diffusion and its subsequent penetration into the high-K gate dielectric may become a problem. It is known by those skilled in the art that the penetration of the boron into the SiO
2
gate dielectric causes a number of problems not only with the quality of the dielectric layer, but especially with the device operation. Boron penetration shifts the threshold voltage of MOS devices to more positive values. The degradation of the MOSFET transconductance and a subthreshold slope is also correlated with boron penetration.
Typically boron is implanted into the polysilicon gate using sufficiently high doses to ensure reasonable conductance of the polysilicon gate. Unfortunately, it is also necessary to activate the dopant with a high-temperature anneal, typically in the range of 950 to 1050° C. in an inert ambient for a few seconds. Boron is an extremely small atom, and as such has a very high diffusion coefficient in both silicon and gate dielectric materials (e.g., SiO
2
and high-K dielectric materials) at such elevated temperatures. During the high-temperature activation annealing, the boron penetrates into and through the gate dielectric. Further with increasing time, significant diffusion of boron occurs, resulting in a build-up of boron at the polysilicon/dielectric interface. Further still, the boron may move from the polysilicon gate into the gate dielectric and into the crystalline silicon substrate. Additionally with increasing time, the boron in the bulk of the polysilicon decreases, while the boron at the polysilicon/dielectric interface increases.
As the boron penetrates into the dielectric layer, a number of measurable effects can be noted. The capacitance-voltage (C-V) curves of a semiconductor device may shift to higher, more positive values as the annealing time is increased. This C-V or flat-band voltage shift (delta V
FB
) which is similar in magnitude to delta V
T
of the MOSFET, degrades device performance.
Boron penetration also effects the quality of the dielectric layer. The yield of devices decreases with increasing boron penetration, which is coincident with increases in delta V
FB
. The yield represents the number of good devices, as measured by their current-voltage characteristics. The reduction in yield resulting from boron penetration could become a substantial impediment to the manufacture of C-MOS devices.
Therefore, there exists a strong need in the art for a device structure which will inhibit boron penetration of a dielectric layer and/or the semiconductor substrate. Thus, the properties of the dielectric layer can be preserved.
SUMMARY OF THE INVENTION
A stacked polysilicon layer may be formed on a high-K gate dielectric of a semiconductor device. The stacked polysilicon layer would include an interface layer. The interface layer would include at least one layer of an oxide material or a nitride rich material. The interface layer may be interposed between a thin polysilicon layer and a thick polysilicon layer. The thin

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