Stacked poly/amorphous silicon gate giving low sheet resistance

Details Stacked poly/amorphous silicon gate giving low sheet resistance Stacked poly/amorphous silicon gate giving low sheet resistance

1999-12-02

2000-08-22

Pham, Long

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438482, 438585, 438657, 438660, H01L 21336

Patent

active

061071471

ABSTRACT:
A method of forming a poly-silicide gate electrode (102). The polysilicon deposition is broken into two steps. After the first polysilicon layer (102a) is formed, a very thin oxide (102b) is formed thereover. Polysilicon deposition then continues to form a second polysilicon layer (102c). The oxide layer (102b) inhibits grain growth resulting in a smaller grain size for the second polysilicon layer (102c). Prior to silicide formation, a pre-amorphization implant is performed to amorphize the second polysilicon layer (102c) and possibly some of the first polysilicon layer (102a) as well. Titanium is deposited and reacted with the polysilicon layers to form a silicide. The silicide process consumes the interface between polysilicon layers (102a & 102c) and possibly a portion of the first polysilicon layer (102a). The resulting silicide layer has a more uniform sheet resistance.

REFERENCES:
patent: 4479831 (1984-10-01), Sandow et al.
patent: 5614428 (1997-03-01), Kapoor
patent: 5837598 (1998-11-01), Aronowitz et al.

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