Stacked load-less static random access memory device

Details Stacked load-less static random access memory device Stacked load-less static random access memory device

2011-08-09

2011-08-09

Quach, Tuan N. (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S401000, C257S758000, C257SE27098

Reexamination Certificate

active

07994582

ABSTRACT:
In a stacked load-less static random access memory (SRAM) device in which a pair of transmission transistors is stacked on a pair of driving transistors, the stacked load-less SRAM device includes first and second transistors arranged in first and second active regions separately on a semiconductor substrate and third and fourth transistors arranged on first and second semiconductor layers over the first and second transistors. A first drain region of the first transistor, a third drain region of the third transistor, and a second gate of the second transistor are electrically connected through a first contact node. A second drain region of the second transistor, a fourth drain region of the fourth transistor, and a first gate of the first transistor are electrically connected through a second contact node.

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