Stacked LDD high frequency LDMOSFET

Details Stacked LDD high frequency LDMOSFET Stacked LDD high frequency LDMOSFET

2001-05-07

2002-12-03

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S286000, C438S307000, C438S546000

Reexamination Certificate

active

06489203

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of high frequency power devices with particular reference to reducing on-resistance while increasing breakdown voltage.
BACKGROUND OF THE INVENTION
High frequency power devices, have become an indispensable part of modern personal communication systems. Among the various power devices, the LDOMOSFET (Lateral Double-diffused metal oxide field effect transistor) is becoming more popular than its bipolar and GaAs counterparts. The desirable characteristics of RF LDMOSFET are a high frequency performance, a low on-state voltage drop, and a high blocking voltage.
The device structure of a conventional RF LDMOS is shown in FIG.
1
. Heavily doped p+ sinker
11
is used to connect the source
12
to the substrate
10
. This enables the source to be led out from the bottom, saving the source bond wire and minimizing the common lead inductance thus offering a better RF performance. An N-LDD (Lightly Doped Drain) region
19
with a shallow junction is used as the drift region. The on-resistance of the conventional high voltage power LDMOS is mainly dominated by the resistance of the voltage sustaining LDD region. The LDMOS blocking capability is mainly determined by the LDD length and doping concentration.
Also shown in
FIG. 1
are polysilicon gate
15
, gate oxide
14
, epitaxially formed P-body
17
, diffusion formed P-body
13
, drain region
18
, and drain contact
16
. Additionally, the output capacitance of the device is schematically shown as capacitor
99
.
Because the doping concentration in the drift region is severely restricted by the blocking voltage, a trade-off exists between high breakdown voltage and low on-state resistance. This trade-off also limits the achievable application frequency of a high voltage RF LDMOSFET. Several approaches to improving the on-state resistance/breakdown voltage tradeoff have been proposed such as, for example, Der-Gao Lin et al. in “A novel LDMOS structure with a step gate oxide” IEDM 1995, pp. 38.2.1-38.2.2. With this approach the length of the drift region can be reduced so that the resistance is lowered without affecting the breakdown voltage.
For high voltage RF LDMOS, in which the drift region constitutes the major source of on-resistance, the main emphasis in improving the transistor performance must be directed towards reducing the LDD resistance. In the present invention a novel RF LDMOS with a stacked LDD structure using existing multiple implant technology is disclosed. Without the need of extra masks, the device was implemented using standard RF LDMOS processing technology.
A routine search of the prior art was performed with the following references of interest being found:
Der-Goa Lin, et al. “A novel LDMOS Structure with a step gate oxide”, IEDM, 1995—pp. 963 to 966. U.S. Pat. No. 5,585,294(Smayuling et al.) shows a DD LDMOS with multiple LDD's. U.S. Pat. No. 5,869,875(Herbert) shows a LDMOS with a trench source contact and sinker. U.S. Pat. No. 6,087,232(Kim et al.), U.S. Pat. No. 6,144,070(Devore et al.) and U.S. Pat. No. 6,118,152(Yamaguchi et al.) show related LDMOS devices and methods.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a LDMOSFET with both higher breakdown voltage and lower on-state resistance than comparable devices of the prior art.
Another object of the invention has been to provide a LDMOSFET with improved high frequency characteristics relative to comparable devices of the prior art.
Still another object has been to provide a process for the manufacture of said improved LDMOSFET.
A further object has been that said manufacturing process be made up of processing steps already in regular use.
These objects have been achieved by changing the composition of the conventional LDD structure that lies between the gate and the drain from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. The upper N type layer is heavily doped to reduce the on-resistance of the device, while the lower N type layer is lightly doped to reduce the output capacitance, thereby improving the high frequency performance. The middle P layer is heavily doped which allows it to bring about pinch-off of the two N layers, thereby raising the device's breakdown voltage.


REFERENCES:
patent: 5585294 (1996-12-01), Smayling et al.
patent: 5869875 (1999-02-01), Hebert
patent: 6087232 (2000-07-01), Kim et al.
patent: 6093609 (2000-07-01), Chuang
patent: 6118152 (2000-09-01), Yamaguchi et al.
patent: 6144070 (2000-11-01), Devore et al.
patent: 6312996 (2001-11-01), Sogo
Der-Gaolin et al., in “A Novel LDMOS Structure with a Step Gate Oxide,” IEDM 1995, pp. 38.2.1-38.2.2, (pp. 963-966).

Affiliated with

Also associated with

Rating

Stacked LDD high frequency LDMOSFET does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stacked LDD high frequency LDMOSFET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked LDD high frequency LDMOSFET will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2987318