Stacked gate structure for flash memory application

Details Stacked gate structure for flash memory application Stacked gate structure for flash memory application

1998-09-16

2000-05-09

Booth, Richard

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257412, 438593, H01L 218247, H01L 29788, H01L 2976, H01L 2994

Patent

active

060607416

ABSTRACT:
In order to form a low resistance gate for use in a flash EPROM or EEPROM, a boron doped amorphous silicon layer is formed on an oxide layer and a layer of tungsten nitride formed thereon. A layer of tungsten silicide is then formed on the tungsten nitride layer acts as a barrier preventing "out diffusion" of a contaminating dopant, e.g., boron, and exhibits good adhesion to the amorphous silicon layer. The tungsten silicide layer, in turn, exhibits good adhesion to the tungsten nitride layer thereby preventing lifting of the silicide layer and dopant penetration.

REFERENCES:
patent: 5536667 (1996-07-01), Cho
patent: 5668394 (1997-09-01), Lur et al.
patent: 5796166 (1998-08-01), Agnello et al.
patent: 5923999 (1999-07-01), Balasubramanyam et al.
patent: 5925918 (1999-07-01), Wu et al.
patent: 5962904 (1999-10-01), Hu

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