Stacked chip package device employing a plurality of lead on chi

Details Stacked chip package device employing a plurality of lead on chi Stacked chip package device employing a plurality of lead on chi

1997-03-04

1998-09-08

Ostrowski, David

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

257686, 257724, 257725, H01L 23495

Patent

active

058048740

ABSTRACT:
A stacked chip package comprising an upper part including an upper semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; an upper lead frame having leads extending over the active surface of the upper semiconductor chip and which are electrically interconnected to the electrode bonding pads of the semiconductor chip; a lower part including a lower semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; a lower lead frame having inner leads extending over the active surface of the lower semiconductor chip which are electrically interconnected to the electrode bonding pads of the lower semiconductor chip, and outer leads for electrical interconnecting the stacked chip package to an external circuit device. The leads of the upper lead frame are formed to directly contact top surfaces of the inner leads of the lower lead frame, so that the upper and the lower parts can be electrically interconnected. An insulating adhesive film is interposed between the upper semiconductor chip and the inner leads of the lower lead frame.

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patent: 5689135 (1997-11-01), Ball

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