Stacked capacitor memory cell and method of manufacture

Details Stacked capacitor memory cell and method of manufacture Stacked capacitor memory cell and method of manufacture

1999-03-26

2000-07-04

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438258, 438396, 438241, 438243, 438399, 438 3, H01L 218242

Patent

active

060837888

ABSTRACT:
A DRAM memory cell structure of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and a stacked capacitor and a method for forming same facilitates low resistance contact between the source/drain of the transistor and a lower electrode of the capacitor. The method in its preferred embodiment uses platinum for the bottom electrode of the capacitor without the need for a diffusion barrier between it and a doped polysilicon plug used to contact the MOSFET. To this end, the formation of the contact is after the deposition of the high dielectric material, such as barium strontium titanate, used to form the dielectric of the capacitor. Also the bottom electrode of the capacitor is partially offset with respect to the polysilicon plug.

REFERENCES:
patent: 5066608 (1991-11-01), Kim et al.
patent: 5266512 (1993-11-01), Kirsch
patent: 5661063 (1997-08-01), Lee
patent: 5793076 (1998-08-01), Fazan et al.
patent: 5828097 (1998-10-01), Tanigawa
patent: 6011284 (2000-01-01), Katori et al.

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