Stacked capacitor dynamic random access memory with a sloped low

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257303, 257775, H01L 2968, H01L 2978, H01L 2992

Patent

active

052162672

ABSTRACT:
A manufacturing method for a DRAM cell provided with a stacked capacitor is disclosed. The method including: (1) defining a switching transistor region by forming a field oxide layer upon a first conduction type semiconductor substrate; (2) forming source and drain regions of a second conduction type; (3) forming respective first conductive layers on a part of said field oxide layer and on a gate oxide layer over a channel region within the switching transistor region; and forming a first insulating layer; (4) forming a second conductive layer and removing parts of the second conductive layer which are over the channel region and the drain region; (5) forming an opening for exposing a part of the source region; (6) forming a third conductive layer on the substrate and overlapping the remaining portions of the second conductive layer, to provide a portion thereof having a saddle structure providing a gentle slope; (7) etching to remove portions of the second and third conductive layers; (8) forming a dielectric layer; and (9) forming a fourth conductive layer.

REFERENCES:
patent: 4951175 (1990-08-01), Kurosawa et al.
patent: 5025294 (1991-06-01), Ema
patent: 5068707 (1991-11-01), Pors et al.

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