Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1993-04-28
1994-04-05
Munson, Gene M.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257303, H01L 2978
Patent
active
053008014
ABSTRACT:
A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations; b) providing a layer of an electrically conductive storage node material within the striated capacitor contact opening; c) removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric having striated sidewalls; d) etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of the external male striated conductive material sidewalls; and e) providing conformal layers of capacitor dielectric and capacitor cell material atop the etched conductive material and over its exposed striated sidewalls. The invention also includes a stacked capacitor construction having an electrically conductive storage node with upwardly rising external sidewalls. Such sidewalls have longitudinally extending striations to maximize surface area and corresponding capacitance in a resulting construction.
REFERENCES:
patent: 5049517 (1991-09-01), Liu et al.
patent: 5068199 (1991-11-01), Sandhu
patent: 5082797 (1992-01-01), Chan et al.
patent: 5110752 (1992-05-01), Lu
patent: 5138411 (1992-08-01), Sandhu
patent: 5227651 (1993-07-01), Kim et al.
T. Ema et al., "3-Dimensional Stacked Capacitor Cell For 16M and 64M DRAMs," IEDM Tech. Digest, pp. 592, 595, 1988.
S. Inoue et al., "A Spread Stacked Capacitor (SSC) Cell For 64 MBit DRAMs," IEDM Tech. Digest, pp. 31-34, 1989.
Blalock Guy
Wald Phillip G.
Micro)n Technology, Inc.
Munson Gene M.
LandOfFree
Stacked capacitor construction does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stacked capacitor construction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked capacitor construction will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-513627