Stacked bottom lead package in semiconductor devices

Details Stacked bottom lead package in semiconductor devices Stacked bottom lead package in semiconductor devices

2000-02-29

2001-06-05

Williams, Alexander O. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With bumps on ends of lead fingers to connect to semiconductor

C257S696000, C257S686000, C257S698000, C257S796000, C257S784000

Reexamination Certificate

active

06242798

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a stacked bottom lead package in semiconductor devices and a method thereof. More specifically, comprising leads that are bent along with the circumference of the body which has been premolded wherein a chip is included inside the premolded body, the package and the method thereof according to the present invention enable a dual process and keep the solder fatigue of the lead from the heat carried via the extended lead and emitted out of the chip and decrease area required for stacking semiconductor packages.
In general, a bottom lead semiconductor package BLP type has leads lie at the bottom of the package body. A method of coupling the leads is Lead On Chip LOC, in which leads have been connected to the chip and then fixed to the chip by molding them simultaneously.
2. Discussion of Related Art
FIG. 1
shows a cross-sectional view of the bottom lead package according to the background art.
The conventional BLP consists of leads
130
fixed to the surface of a semiconductor chip
120
with an adhesive tape
140
, input/output pads of the chip
120
, leads
130
and bonding wires
150
wherein the portion of the inner leads of the leads
130
and the input/output pads of the chip
120
are connected electrically each other, and a molded part
110
including the bonding wire
150
and having been formed by means of pouring epoxy resin into it.
As a portion of the leads
130
, outer leads are disclosed under the bottom of the molded part
110
and the bottom of the molded part
110
and the surface of the leads are located at the same plane, the BLP is mounted on a printed circuit board at which the disclosed portion of the leads
130
are soldered.
FIG. 2
is a flow chart showing the process of fabricating the BLP according to the background art.
As is shown in
FIG. 2
, the conventional process of fabricating the BLP comprises the steps of separating a wafer including a plurality of chips into each chip by means of cutting the wafer S
10
, a die bonding fixing the separated chip to a paddle of a lead frame S
20
, a wire bonding S
30
connecting electrically the chip to the leads with bonding-wires between the input/output pads and the leads, a molding S
40
forming a molded part in which the wire-bonded chip and the leads are coupled with each other in use of an epoxy resin, hardening the molded body S
50
, a grinding S
60
eliminating the epoxy molding compound which has remained at the disclosed leads in the molding step, a plating S
70
soldering the disclosed leads with protecting materials, a marking S
80
giving an identification factor on a surface of the molded part, a lead trimming and a forming S
90
which are eliminating an unnecessary portion of the leads out of the molded part and bending the leads according to a defined pattern, respectively.
FIG. 3A
to
FIG. 3B
show variations of formed leads to stack semiconductor packages.
In
FIG. 3A
, a TSOP typed semiconductor package is formed by means of making outer leads of the upper stacked semiconductor package longer than those of the lower stacked semiconductor package.
In
FIG. 3B
, the leads of the stacked semiconductor packages are coupled with connecting bars
160
.
The conventional BLP has been troubled with the fatigue occurring on account of the heated solder formed on the surface of the leads wherein the heating is caused by the heat emitted out of the chip and carried via leads, and the poor durability of the semiconductor resulted from the micro gap that has been caused by the shock of cutting the leads on account of the short distance between the leads and the molded part.
And the conventional method of fabricating a BLP has problems in time consuming on the whole process in consecutive order such as a process after another, and in additive process of grinding the leads to eliminate the epoxy molding compounds that has remained at the leads in molding.
Moreover, in stacking the semiconductor packages according to the conventional method, the interfaces between the outer leads protrude outward and lead bars are necessary for connecting each lead together, causing the increase of mounting area and the increased height of stacking the semiconductor packages due to the insufficient contacts between the interfaces of the leads.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the above problems in stacked bottom lead package in semiconductor devices.
Therefore, it is an object of the present invention to provide a shortened processing time and a decreased solder fatigue, wherein the processing time is shortened by means of the dual processes in which an independent process for forming a premolded body from the main process is executed and the solder fatigue is decreased by means of having a distance between the leads and the chip enough to keep the heat of the chip from being carried and bending the leads along with the circumference of the premolded body.
Another object of the present invention is to provide general semiconductor packages having various types of leads and a minimized area and height required for stacking semiconductor packages by means of elongating the leads around the portion of the body of the semiconductor package to increase contacting areas.
In achieving the above object, the present invention comprises a chip having a plurality of input/output pads, a body sealing up the body, a plurality of leads having one end of each lead connected to a plurality of the chip, having the other end of each lead protrude out of a front face of the body and extend to a back face of the body, at least lying closely on a front face and a lateral face of body and a material fixing a plurality of the leads to the chip.
And a method to provide the present invention comprises fixing one end of each lead to a semiconductor chip, connecting a plurality of pads of the chip respectively to the one end of said each lead with a plurality of wires, forming a body embracing the chip and the one end of the each lead by means of molding with resin wherein a portion of the each lead is disclosed toward same direction of front faces of a plurality of the pads of the chip having the same direction of a front face of the body, and bending the other end of the each lead extending to a back face of the body.
And also stacked semiconductor packages comprises a first unit package including a chip having a plurality of leads, a body sealing up the chip, a plurality of leads having one end of each the lead connected to a plurality of the chip, having the other end of each lead protrude out of a front face of the body and extend to a back face of the body, at least lying closely on a front face and a lateral face of the body, and a material fixing a plurality of the leads to the chip, and a second unit package having a plurality of leads connected electrically to a plurality of the leads of the first unit package, stacked on the first unit package.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


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patent: 6

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