Stack type semiconductor chip package having different type...

Details Stack type semiconductor chip package having different type... Stack type semiconductor chip package having different type...

2007-12-07

2009-11-17

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S723000, C257S433000, C257SE23010

Reexamination Certificate

active

07619315

ABSTRACT:
A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.

REFERENCES:
patent: 5633530 (1997-05-01), Hsu
patent: 5869896 (1999-02-01), Baker et al.
patent: 6424031 (2002-07-01), Glenn
patent: 6559539 (2003-05-01), Tu et al.
patent: 6882021 (2005-04-01), Boon et al.
patent: 2003-0057203 (2003-07-01), None
patent: 2006-0005720 (2006-01-01), None
English language abstract of Korean Publication No. 2003-0057203.
English language abstract of Korean Publication No. 2006-0005720.

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