Stack gate with tip vertical memory and method for...

Details Stack gate with tip vertical memory and method for... Stack gate with tip vertical memory and method for...

2006-04-04

2006-04-04

Parker, Kenneth (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S201000, C438S257000, C438S260000, C438S262000, C438S267000

Reexamination Certificate

active

07022573

ABSTRACT:
A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

REFERENCES:
patent: 5468663 (1995-11-01), Bertin et al.
patent: 5705415 (1998-01-01), Orlowski et al.
patent: 6255689 (2001-07-01), Lee
patent: 6444525 (2002-09-01), Lee
patent: 6781191 (2004-08-01), Lin
patent: 6818948 (2004-11-01), Lin

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