Stack DRAM cell manufacturing process with high capacitance capa

Details Stack DRAM cell manufacturing process with high capacitance capa Stack DRAM cell manufacturing process with high capacitance capa

1997-06-04

1998-10-20

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438397, H01L 218242

Patent

active

058245820

ABSTRACT:
A method is disclosed for a manufacturing process of forming a high capacitance capacitor in a DRAM cell. A semiconductor substrate having a switching MOS transistor comprising a word line and a bit line is provided. A first dielectric is deposited over the substrate and planarized. Contact hole is etched in the first dielectric until the substrate is exposed. A doped first polysilicon is blanket deposited over the substrate filling the holes. A trench is next formed partially in the first polysilicon layer over the contact hole but not reaching the hole. A second dielectric material is deposited over the substrate filling the trench. The dielectric layer is then plasma etched back so as to form a dielectric plug in the trench. Using now the dielectric plug as a mask, the first polysilicon layer is then removed to a predetermined thickness by means of reactive ion etch. A second polysilicon is next formed conformally over the first polysilicon layer covering the dielectric plug. Subsequently, the second polysilicon is etched back so as to form a (second) polysilicon spacer around the dielectric plug. Finally, the dielectric plug is removed to leave behind a hollow trench with second polysilicon walls and first polysilicon base. The storage electrode is completed by covering the resulting structure with a third conformal dielectric and then filling with a third polysilicon. The plate of the capacitor is formed by patterning the third polysilicon.

REFERENCES:
patent: 5217914 (1993-06-01), Matsumoto et al.
patent: 5403767 (1995-04-01), Kim
patent: 5453633 (1995-09-01), Yun
patent: 5491103 (1996-02-01), Ahn et al.
patent: 5677221 (1997-10-01), Tseng
patent: 5677223 (1997-10-01), Tseng

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