Stable memory cell with improved operation speed

Details Stable memory cell with improved operation speed Stable memory cell with improved operation speed

2007-04-17

2007-04-17

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S202000

Reexamination Certificate

active

10906030

ABSTRACT:
A memory cell, including a word line, a bit line, a first node storing a bit value voltage level, a driver transistor coupled between the first node and a ground level, and at least one data transfer transistor having a gate electrode coupled to the word line, a source electrode coupled to the bit line, and a drain electrode coupled to the first node, wherein a channel length of the at least one data transfer transistor is smaller than a channel length of the driver transistor. By making the channel length of a data transfer transistor smaller than that of a driver transistor to which the data transfer transistor is coupled, operation speed and in particular read operation speed of the memory cell is improved, while maintaining memory cell stability.

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