SRAM with SIPOS resistor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257537, 257538, 257646, 257904, H01L 2711

Patent

active

057510431

ABSTRACT:
A method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises formation of a polysilicon 1 layer on said semiconductor substrate. The polysilicon 1 layer is patterned and etched. An interpolysilicon layer is formed over the polysilicon 1 layer, patterned and etched forming an opening through the interpolysilicon layer exposing a contact area on the surface of the polysilicon 1 layer. A SIPOS layer forms a resistor material over the interpolysilicon layer in contact with the polysilicon 1 layer through the opening. A load resistor mask is formed over a load resistor region to be formed in the SIPOS layer, and ions are implanted in the remainder of the SIPOS layer not covered by the load resistor mask to convert the remainder of the SIPOS layer from a resistor into an interconnect structure integral with a load resistor in the load resistor region.

REFERENCES:
patent: 4176372 (1979-11-01), Matsushita et al.
patent: 4533935 (1985-08-01), Mochizuki
patent: 4717681 (1988-01-01), Curran
patent: 4950620 (1990-08-01), Harrington, III
patent: 4961103 (1990-10-01), Saitoh et al.
patent: 4965214 (1990-10-01), Choi et al.
patent: 5200356 (1993-04-01), Tanaka
patent: 5616951 (1997-04-01), Liang
Sze, "VLSI Technology" McGraw Hill International Editions p. 248.

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