SRAM memory structure and manufacturing method thereof

Details SRAM memory structure and manufacturing method thereof SRAM memory structure and manufacturing method thereof

1994-02-09

1995-01-24

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365154, G11C 1300

Patent

active

053847318

ABSTRACT:
The invention provides an SRAM memory cell structure permitting increase of integration density while maintaining operation stability. A memory cell in the SRAM includes a pair of access transistors, a pair of driver transistors, and a pair of load transistors. The gate insulating film of access transistor is formed of a single layer of silicon oxide film, while the gate insulating film of driver transistor is formed of a stacked layer formed of a silicon oxide film and a silicon nitride film. The pair of load transistors are formed of two layers of polycrystalline silicon layers stacked upon each other with an insulating film therebetween. A source region and a drain region are formed in each of polycrystalline silicon layers with each channel region therebetween. One drain region forms a gate opposite to the other channel region, while the other drain region forms a gate opposite to the one channel region.

REFERENCES:
patent: 4835740 (1989-05-01), Sato
"16Mbit SRAM Cell Technologies for 2.0V Operation", Ohkubo et al. International Electron Devices Meeting 1991 Technical Digest pp. 481-484.
"Submicron Device I", Mitsumasa Koyanagi, Maruzen Kabushiki Kaisha, pp. 4-8.
"Static-Noise Margin Analysis of MOS SRAM Cells", Evert Seevinck, IEEE Journal of Solid-State Circuits, vol. sc-22, No. 5. Oct. 1987, pp. 748-754.
"Parasitic Resistance Effects on Static MOS RAM", Shinohara et al. VLSI '82, pp. 106-107.
"A 4-Mb CMOS SRAM with a PMOS Thin-Film-Transistor Load Cell", Ootani et al., IEEE Journal of Solid-State Circuits, vol. 25, No. 5, pp. 1082-1092.

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