Method and apparatus for scan testing with extended test vector

Details Method and apparatus for scan testing with extended test vector Method and apparatus for scan testing with extended test vector

1995-04-17

1998-06-02

Lall, Pavshotam S.

39518306, G06F 1126

Patent

active

057614890

ABSTRACT:
A data processor (12) has built-in circuitry for scan testing certain circuits. The data processor generates and stores test vectors in a memory system (22) normally used for data and instruction storage. These vectors can be much larger than the size of any scan chain. During testing, the stored vectors are automatically routed to the circuits to be tested (36, 38) and the outputs compared to a benchmark. The data processor (12) need not pause to generate additional test vectors. Therefore, the data processor (12) can use a single circuit to generate scan data and compress scan results with minimal timing or size implications.

REFERENCES:
patent: 4827476 (1989-05-01), Garcia
patent: 5173906 (1992-12-01), Dreibel et al.
patent: 5175494 (1992-12-01), Yoshimori
patent: 5383143 (1995-01-01), Crouch et al.
patent: 5553082 (1996-09-01), Connor et al.
James Broseghini, et al., An ALU-Based Programmable MISR/Pseudorandom Generator for a MC67HC11 Family Self-Test, Proceedings of the Int'l. Test Conf., Baltimore, Oct. 17-21, 1993, pp. 349-358.

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