SRAM memory cell with reduced internal cell voltage

Details SRAM memory cell with reduced internal cell voltage SRAM memory cell with reduced internal cell voltage

1995-03-31

1996-08-06

Nguyen, Tan T.

Static information storage and retrieval

Systems using particular element

Flip-flop

365185070, G11C 1140

Patent

active

055440975

ABSTRACT:
A memory cell having a first device operable to selectively conduct and coupled between a first cell node and a low voltage reference node and a second device operable to selectively conduct and coupled between a second cell node and the low voltage reference node. The memory cell further includes a first and second data line and circuitry for receiving a system level voltage and for biasing the first and second data lines at a first and second data voltage, respectively. Still further, the memory cell includes circuitry for coupling the first and second data line to the first and second cell node, respectively, such that a logical high voltage is selectively written to one of the first and second cell nodes while a logical low is written to the other of the first and second cell nodes during a write operation. Still further, the memory cell includes a voltage source node for receiving a cell voltage and circuitry for coupling the voltage source node to the first and second cell nodes. Lastly, the memory cell includes cell voltage circuitry for generating the cell voltage, wherein the cell voltage circuitry is operable to output a cell voltage less than the system level voltage.

REFERENCES:
patent: 5452246 (1995-09-01), Kawashima

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